GD31244 Intel Corporation, GD31244 Datasheet
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R ® Intel 852GME Chipset GMCH ® and Intel 852PM Chipset MCH Datasheet June 2003 Document Number: 253027-001 ...
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... Intel Corporation www.intel.com or call 1-800-548-4725 Intel, Pentium, Celeron, Enhanced Intel SpeedStep and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2003, Intel Corporation 2 ® ...
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R Contents 1 Overview ........................................................................................................................... 17 1.1 Terminology.......................................................................................................... 17 1.2 Reference Documents.......................................................................................... 19 1.3 System Architecture Overview ............................................................................. 20 1.3.1 1.3.2 1.4 Processor Host Interface...................................................................................... 20 1.4.1 1.5 Intel 852PM and 852GME DDR SDRAM Interface .............................................. 21 1.6 GMCH Internal ...
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Register Description.......................................................................................................... 63 3.1 Conceptual Overview of the Platform Configuration Structure ............................ 63 3.2 Nomenclature for Access Attributes..................................................................... 64 3.3 Standard PCI Bus Configuration Mechanism....................................................... 65 3.4 Routing Configuration Accesses .......................................................................... 65 3.4.1 3.4.2 3.4.3 3.5 Register Definitions .............................................................................................. ...
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R 3.8 Main Memory Control, Memory I/O Control Registers (Device #0, Function #1)........................................................................................................ 104 3.8.1 3.8.2 3.8.3 3.8.4 3.8.5 3.8.6 3.8.7 3.8.8 3.8.9 3.8.10 3.8.11 3.8.12 3.8.13 3.8.14 3.8.15 3.8.16 3.8.17 3.9 Configuration Process Registers (Device #0, Function #3) ............................... ...
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MLIMIT1 - Memory Limit Address Register (Device #1) .................... 144 3.10.18 PMBASE1 - Prefetchable Memory Base Address Reg (Device #1) .. 145 3.10.19 PMLIMIT1 - Prefetchable Memory Limit Address Reg (Device #1) ... 146 3.10.20 BCTRL - Bridge Control ...
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R 5.3.2 5.3.3 5.3.4 5.4 Integrated Graphics Overview............................................................................ 180 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.5 Display Interface................................................................................................. 193 5.5.1 5.5.2 5.6 AGP Interface Overview..................................................................................... 199 5.6.1 5.6.2 5.6.3 5.6.4 5.7 Power and Thermal Management...................................................................... 204 5.8 General ...
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Figures Figure 1. Intel 852PM GMCH Chipset System Block Diagram......................................... 13 Figure 2. Intel 852GME GMCH Chipset System Block Diagram...................................... 16 Figure 3 . Full and Warm Reset Waveforms..................................................................... 53 Figure 4. Configuration Address Register......................................................................... 68 Figure 5. Configuration Data ...
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R Tables Table 1. SDRAM Memory Capacity .................................................................................. 22 Table 2. Intel 852GME GMCH Interface Clocks ............................................................... 25 Table 3. Host Interface Signal Descriptions...................................................................... 28 Table 4. DDR SDRAM Interface Descriptions .................................................................. 31 Table 5. AGP Addressing Signal Descriptions ................................................................. ...
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Table 49. XOR Chains Exclusion list .............................................................................. 210 Table 50. XOR Mapping ................................................................................................. 211 Table 51. Voltage Levels and Ball Out for Voltage Groups ............................................ 222 Table 52. State of Power Planes in C/S States .............................................................. 225 Table 53. Strapping ...
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R Revision History Document No. 253027 ® Intel 852GME Chipset GMCH & Intel Rev. No. Description -001 Initial release ® 852PM Chipset MCH Datasheet Rev. Date June 2002 11 ...
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Intel 852PM Chipset MCH Features Processor/Host Bus Support ® Mobile Intel Pentium ® ® Intel Celeron Source synchronous double pumped Address (2X) Source synchronous quad pumped Data (4X) Supports a subset of the Enhanced Mode Scalable Bus Protocol Intel ...
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R Figure 1. Intel 852PM GMCH Chipset System Block Diagram AGP Controller ATA100 IDE (2) USB 2.0/1.1 (6) Audio Codec Audio Codec ® Intel 852GME Chipset GMCH & Intel Intel Processor 400/533MHz AGP 2.0 852PM MCH 732 Micro-FCBGA 266 MHz ...
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Intel 852GME Chipset GMCH Features ® Note: The Intel 852GME chipset GMCH shares the same chipset features as the Intel 852PM chipset MCH along with the following additional integrated graphics features. Memory System ECC not supported with AGP Integrated ...
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R supported Max 165-MHz dot clock Variety of DVO devices supported Compliant with DVI Specification 1.0 Dedicated LFP LVDS interface Single or dual channel LVDS panel support up UXGA panel resolution with frequency range from 25-MHz to 112- MHz (single ...
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Figure 2. Intel 852GME GMCH Chipset System Block Diagram CRT Panel DVO Device/ AGP Graphic Controller ATA100 IDE (2) USB 2.0/1.1 (6) Audio Codec Audio Codec 16 Intel Processor RGB 400/533 MHz PSB LVDS 852GME GMCH 732 Micro-FCBGA DVO/AGP 266 ...
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R 1 Overview This datasheet provides Intel’s specifications for the Intel based systems. The Intel 852PM chipset MCH is designed for use with the mobile Intel ® ® the Intel Celeron processor. The Intel MCH manages the flow of information ...
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Overview Term DVMT EDID Full Reset GMCH Hub Interface (HI) Host IGD Intel® 852GME GMCH Intel® 852PM MCH Intel® 852 chipset Family Intel® 82801DBM ICH4-M IPI LFP LVDS MSI PSB PWM SSC System Bus UMA 18 Intel Description Dynamic Video ...
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R Term VDL Primary PCI AGP AGP/PCI1 GART GTLB 1.2 Reference Documents ® Mobile Intel Pentium Datasheet ® ® Intel Celeron Processor on 0.13 Micron Processor Datasheet PCI Local Bus Specification 2.2 ® Intel 82801DBM I/O Controller Hub 4 Mobile ...
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Overview 1.3 System Architecture Overview 1.3.1 Intel 852GME GMCH System Architecture The Intel 852GME GMCH component provides the processor interface, DDR SDRAM interface, display interface, and hub interface in an Intel 852GME chipset platform. The GMCH is optimized for use ...
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R AGTL+ termination resistors on all of the AGTL+ signals 32-bit host bus addressing allowing the CPU to access the entire the memory address space The GMCH/MCH has a 12-deep In-Order Queue to support up to twelve ...
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Overview Table 1. SDRAM Memory Capacity Technology 128 Mb 256 Mb 512 Mb 128 Mb 256 Mb 512 Mb The Intel 852PM MCH and Intel 852GME system memory interface supports a thermal throttling scheme to selectively throttle reads and/or writes. ...
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R The GMCH has four display ports, one analog and three digital. These provide support for a progressive scan analog monitor, a dedicated dual channel LVDS panel and two DVO devices. The data that is sent out to the display ...
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Overview within the Graphics Aperture address range pass through an address translation mechanism with a fully associative 20 entry TLB. Accesses between AGP and hub interface are limited to memory writes originating from the hub interface destined for AGP. The ...
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R AGP and hub interface run at a constant 66-MHz base frequency. The hub interface runs at 4x, while AGP transfers may be at 1x, 2x, or 4x. The following table indicates the frequency ratios between the various interfaces that ...
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Overview 26 Intel This page intentionally left blank. ® 852GME Chipset GMCH & Intel ® 852PM Chipset MCH Datasheet R ...
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R 2 Signal Description This section describes the GMCH/MCH signals. These signals are arranged in functional groups according to their associated interface. The following notations are used to describe the signal type: I Input pin O Output pin I/O Bi-directional ...
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Signal Description 2.1 Host Interface Signals Table 3. Host Interface Signal Descriptions Signal Name ADS# AGTL+ BNR# AGTL+ BPRI# AGTL+ BREQ0# AGTL+ CPURST# AGTL+ DBSY# AGTL+ DEFER# AGTL+ DINV[3:0]# AGTL+ DPSLP# 28 Intel Type I/O Address Strobe: The system bus ...
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R Signal Name DRDY# AGTL+ HA[31:3]# AGTL+ HADSTB[1:0]# AGTL+ HD[63:0]# AGTL+ HDSTBP[3:0]# AGTL+ HDSTBN[3:0]# HIT# AGTL+ HITM# AGTL+ HLOCK# AGTL+ HREQ[4:0]# AGTL+ HTRDY# AGTL+ ® Intel 852GME Chipset GMCH & Intel Type Note that this is a low-voltage CMOS buffer ...
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Signal Description Signal Name RS[2:0]# AGTL+ 30 Intel Type O Response Status: Indicates the type of response according to the following the table: RS[2:0]# Response type 000 Idle state 001 Retry response 010 Deferred response 011 Reserved (not driven by ...
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R 2.2 DDR SDRAM Interface Table 4. DDR SDRAM Interface Descriptions Signal Name SCS[3:0]# SSTL_2 SMA[12:0] SSTL_2 SBA[1:0] SSTL_2 SRAS# SSTL_2 SCAS# SSTL_2 SWE# SSTL_2 SDQ[71:0] SSTL_2 ® Intel 852GME Chipset GMCH & Intel Type O Chip Select: These pins ...
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Signal Description SDQS[8:0] SSTL_2 SCKE[3:0] SSTL_2 SMAB[5,4,2,1] SSTL_2 SDM[8:0] SSTL_2 RCVENOUT# SSTL_2 RCVENIN# SSTL_2 32 Intel I/O Data Strobes: Data strobes are used for capturing data. During writes, SDQS is centered on data. During reads, SDQS is edge aligned with ...
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R 2.3 AGP Interface Signals Unless otherwise specified, the voltage level for all signals in this interface is 1.5 volts. 2.3.1 AGP Addressing Signals Table 5. AGP Addressing Signal Descriptions Signal Type Name I GPIPE# AGP I GSBA[7:0] AGP The ...
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Signal Description 2.3.2 AGP Flow Control Signals Table 6. AGP Flow Control Signals Signal Type Name I GRBF# AGP I GWBF# AGP 34 Intel Description Read Buffer Full: Read buffer full indicates if the master is ready to accept previously ...
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R 2.3.3 AGP Status Signals Table 7. AGP Status Signal Descriptions Signal Type Name O GST[2:0] AGP ® Intel 852GME Chipset GMCH & Intel Description Status: Provides information from the arbiter to an AGP Master on what it may do. ...
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Signal Description 2.3.4 AGP Strobes Table 8. AGP Strobe Descriptions Signal Type Name I/O GADSTB[0] AGP I/O GADSTB#[0] AGP I/O GADSTB[1] AGP I/O GADSTB#[1] AGP GSBSTB AGP GSBSTB# AGP 36 Intel Description Address/Data Bus Strobe-0: provides timing for 2x and ...
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R 2.3.5 AGP/PCI Signals-Semantics For transactions on the AGP interface carried using AGP FRAME# protocol these signals operate similarly to their semantics in the PCI 2.1 specification, as defined below. Table 9. AGP/PCI Signals-Semantics Descriptions Signal Type Name I/O GFRAME# ...
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Signal Description Signal Type Name I/O GSTOP# AGP I/O GDEVSEL# AGP I GREQ# AGP O GGNT# AGP I/O GAD[31:0] AGP I/O GCBE#[3:0] AGP 38 Intel Description G_STOP#: Stop. During PIPE# and SBA Operation: This signal is not used during PIPE# ...
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R Signal Type Name I/O GPAR AGP PCIRST# from the ICH4-M is assumed to be connected to RSTIN# and is used to reset AGP interface logic within the GMCH/MCH. The AGP agent will also typically use PCIRST# provided by the ...
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Signal Description 2.5 Clocks Table 11. Clock Signals Signal Name BCLK BCLK# SCK[5:0] SSTL_2 SCK[5:0]# SSTL_2 GCLKIN DVOBCLK DVOBCLK# DVOCCLK DVOCCLK# 40 Intel Type Host Processor Clocking I Differential Host Clock In: These pins receive a buffered host clock from ...
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R DVOBCCLKINT DPMS DREFCLK DREFSSCLK ® Intel 852GME Chipset GMCH & Intel I DVOBC Pixel Clock Input/Interrupt: DVO This input can be programmed to be either a TV reference clock input from a TV encoder or an Interrupt input pin ...
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Signal Description 2.6 GMCH Internal Graphics Display Signals The Intel 852GME internal graphics device has support for four display ports: a dedicated LVDS panel interface, two DVO ports, and an analog VGA port. 2.6.1 Dedicated LVDS Panel Interface Table 12. ...
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R 2.6.2 Digital Video Port B (DVOB) Table 13. Digital Video Port B Signal Descriptions Signal Name Type DVOBD[11:0] DVOBHSYNC DVOBVSYNC DVOBBLANK# DVOBFLDSTL ® Intel 852GME Chipset GMCH & Intel O DVOB Data: This data bus is used to drive ...
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Signal Description 2.6.3 Digital Video Port C (DVOC) Table 14. Digital Video Port C Signal Descriptions Signal Name DVOCD[11:0] DVOCHSYNC DVOCVSYNC DVOCBLANK# DVOCFLDSTL 44 Intel Type O DVOC Data: This data bus is used to drive 12-bit RGB data on ...
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R Table 15. DVOB and DVOC Port Common Signal Descriptions Signal Name DVOBCINTR# ADDID[7:0] Signal Name DVODETECT ® Intel 852GME Chipset GMCH & Intel Type I DVOBC Interrupt: This pin is used to signal an interrupt, typically used to indicate ...
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Signal Description 2.6.4 GMCH DVO & I2C to AGP Pin Mapping The GMCH will mux a DVODETECT signal with the GPAR signal on the AGP bus. This signal will act as a strap and indicate whether the interface is in ...
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R 2.6.5 Analog Display Table 17. Analog Display Signal Descriptions Signal Type Name O VSYNC CMOS O HSYNC CMOS O RED Analog O RED# Analog O GREEN Analog O GREEN# Analog O BLUE Analog O BLUE# Analog ® Intel 852GME ...
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Signal Description 2.6.6 Graphics General Purpose Input/Output Signals Table 18. Graphics GPIO Signal Descriptions GPIO I/F Total AGPBUSY# EXTTS_0 PANELVDDEN PANELBKLTEN PANELBKLTCTL LCLKCTLA LCLKCTLB DDCACLK DDCADATA DDCPCLK DDCPDATA MI2CCLK 48 Intel Type O AGPBUSY: Output of the GMCH IGD to ...
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R GPIO I/F Total MI2CDATA MDVICLK MDVIDATA MDDCDATA MDDCCLK 2.7 Power Sequencing Signal Description GPIO I/F Total RSTIN# PWROK ® Intel 852GME Chipset GMCH & Intel Type I/O DVO I2C Data: This signal is used as the I2C_DATA for a ...
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Signal Description 2.8 Voltage References, PLL Power Table 19. Voltage References, PLL Power GPIO I/F Total HXRCOMP HYRCOMP HXSWING HYSWING HDVREF[2:0] HAVREF HCCVREF VTTLF VTTHF SMRCOMP SMVREF_0 SMVSWINGH SMVSWINGL VCCSM VCCQSM 50 Intel Type Host Processor Analog Host RCOMP: Used ...
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R Power VCCASM HLRCOMP PSWING HLVREF VCCHL DVORCOMP GVREF VCCDVO GPIO VCCGPIO REFSET VCCADAC VSSADAC LIBG VCCDLVDS VCCTXLVDS VCCALVDS VSSALVDS VCCAHPLL VCCAGPLL VCCADPLLA VCCADPLLB VCC VSS ® Intel 852GME Chipset GMCH & Intel Power supply for system memory logic running ...
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Signal Description 2.9 Reset States and Pull-up/Pull-downs This section describes the expected states of the Intel 852GME GMCH and 852PM MCH I/O buffers. These tables refer only to the contributions on the interface from the GMCH/MCH and do NOT reflect ...
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R 2.9.1 Full and Warm Reset State Figure 3 . Full and Warm Reset Waveforms ICH4-M Power ICH4-M PWROK In ICH4-M PCIRST# Out GMCH/MCH RSTIN# In GMCH/MCH CPURST# Out GMCH/MCH Power GMCH/MCH PWROK In GMCH/MCH Reset State Unknown All register ...
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Signal Description Table 21. Host Signal Reset and Power Managed States Before CPURST# Host I/F Total ADS# Term H BNR# Term H BPRI# Term H BREQ0# Low CPURST# Low DBSY# Term H DEFER# Term H DINV[3:0]# Term H DPWR# Low ...
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R Table 22. System Memory Signal Reset and Power Managed States Before CPURST# Host I/F Total Hi-Z SDQ[63:0] Hi-Z SDM[8:0] Hi-Z SDQS[7:0] Hi-Z SCK[5:0] Hi-Z SCK[5:0]# Hi-Z SMA[12:0] Hi-Z SMAB_5,4,2,1 Hi-Z SBA_1:0 Hi-Z SRAS# Hi-Z SCAS# Hi-Z SWE# Hi SCS[3:0]# ...
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Signal Description Table 23. Hub Interface Signal Reset and Power Managed States Before CPURST# Host I/F Total Term L HL[7:0] Term L HL[10] Term L HLSTB TermL HLSTB# Input HL[9] Low HL[8] 56 Intel Just out of Deassertion CPURST# Term ...
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R Table 24. GMCH DVO Signal Reset and Power Managed States Before CPURST# Host I/F Total DVOCCLK# DVOBCLK# Hi-Z DVOBHSYNC Hi-Z DVOBVSYNC Hi-Z DVOBD[1] Hi-Z DVOBD[0] Hi-Z DVOBD[3] Hi-Z DVOBD[2] Hi-Z DVOBD[5] Hi-Z DVOBD[4] Hi-Z DVOBD[6] Hi-Z DVOBD[9] Hi-Z DVOBD[8] ...
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Signal Description Before CPURST# Host I/F Total DVOBFLDSTL Input MDDCDATA Hi-Z External PU DVOCVSYNC Hi-Z DVOCHSYNC Hi-Z DVOCBLANK# Hi-Z DVOCD[0] Hi-Z DVOCD[1] Hi-Z DVOCD[2] Hi-Z DVOCD[3] Hi-Z DVOCD[4] Hi-Z DVOCD[7] Hi-Z DVOCD[6] Hi-Z DVOCD[8] Hi-Z DVOCD[11] Hi-Z DVOCD[10] Hi-Z DVOBCINTR# ...
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R Before CPURST# Host I/F Total DVOCFLDSTL Input DVOBD[7] Hi-Z DVOBBLANK# Hi-Z DVOCD[5] Hi-Z MI2CDATA Hi-Z External PU MDVIDATA Hi-Z External PU MI2CCLK Hi-Z External PU MDDCCLK Hi-Z External PU MDVICLK Hi-Z External PU DPMS Input ® Intel 852GME Chipset ...
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Signal Description Table 25. GMCH GPIO Signal Reset and Power Managed States Before CPURST# Host I/F Total Hi RSTIN# Hi PWROK Low HSYNC Low VSYNC External PU AGPBUSY# External PU EXTTS_0 PU LCLKCTLA PU LCLKCTLB Hi-Z PANELVDDEN PANELBKLTE Hi-Z N ...
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R Table 26. GMCH LVDS Signal Reset and Power Managed States Before CPURST# Host I/F Total Drive-VSS IYAP[3:0] Drive-VSS IYAM[3:0] Drive-VSS ICLKAP Drive-VSS ICLKAM Drive-VSS IYBP[3:0] Drive-VSS IYBM[3:0] Drive-VSS ICLKBP Drive-VSS ICLKBM ® Intel 852GME Chipset GMCH & Intel Just ...
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Signal Description 62 Intel This page intentionally left blank. ® 852GME Chipset GMCH & Intel ® 852PM Chipset MCH Datasheet R ...
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R 3 Register Description 3.1 Conceptual Overview of the Platform Configuration Structure The Intel 852GME GMCH, Intel 852PM MCH and ICH4-M are physically connected by hub interface. From a configuration standpoint, the hub interface is logically PCI bus #0. As ...
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Register Description Table 27. Device Number Assignment GMCH/MCH Function Host-Hub Interface, DDR SDRAM I/F, Legacy control Host-to-AGP Bridge(Virtual PCI-to-PCI) Integrated Graphics Controller (IGD) 3.2 Nomenclature for Access Attributes Table 28 provides the nomenclature for the access attributes. Table 28. Assignment ...
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R A physical PCI Bus #0 does not exist. The hub interface and the internal devices in the GMCH/MCH and ICH4-M logically constitute PCI Bus #0 to configuration software. 3.3 Standard PCI Bus Configuration Mechanism The PCI bus defines a ...
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Register Description The Host-Hub Interface Bridge entity within the GMCH/MCH is hardwired as Device #0 on PCI Bus #0. The Host-AGP/PCI_B Bridge entity within the GMCH/MCH is hardwired as Device #1 on PCI Bus #0. Configuration cycles to any of ...
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R Note: Although initial AGP platform implementations will not support hierarchical buses residing below AGP, this specification still must define this capability in order to support PCI-66 compatibility. Note also that future implementations of the AGP devices may support hierarchical ...
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Register Description DDR SDRAM configurations, operating parameters, and optional system features that are applicable and to program the GMCH/MCH registers accordingly. 3.6 I/O Mapped Registers The GMCH/MCH contains two registers that reside in the CPU I/O Address Space: the Configuration ...
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R Bit 31 Configuration Enable (CFGE): When this bit is set to 1, accesses to PCI Configuration Space are enabled. If this bit is Reset to 0, accesses to PCI Configuration Space are disabled. 30:24 Reserved 23:16 Bus Number: When ...
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Register Description 3.6.2 CONFIG_DATA – Configuration Data Register I/O Address: Default Value: Access: Size: CONFIG_DATA is a 32-bit Read/Write window into Configuration Space. The portion of Configuration Space that is referenced by CONFIG_DATA is determined by the contents of CONFIG_ADDRESS. ...
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R 3.7 Host-Hub Interface Bridge Device Registers (Device #0, Function #0) Table 29 summarizes the configuration space for Device #0, Function#0. Table 29. GMCH/MCH Configuration Space - Device #0, Function#0 Register Name Vendor Identification Device Identification PCI Command PCI Status ...
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Register Description Register Name System Management RAM Control Extended System Management RAM Control Error Status Error Command SMI Command SCI Command Secondary Host Interface Control Register AGP Capability Identifier AGP Status Register AGP Command AGP Control AGP Functional Aperture Translation ...
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R 3.7.1 VID – Vendor Identification Register (Device #0) Address Offset: Default Value: Access: Size: The VID register contains the vendor identification number. This 16-bit register, combined with the Device Identification Register, uniquely identifies any PCI device. Writes to this ...
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Register Description 3.7.3 PCICMD – PCI Command Register (Device #0) Address Offset: Default Value: Access: Size: Since GMCH/MCH Device #0 does not physically reside on PCI_A many of the bits are not implemented. Bit 15:10 Reserved 9 Fast Back-to-Back Enable ...
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R 3.7.4 PCI Status Register (Device #0) Address Offset: Default Value: Access: Size: PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0’s PCI Interface. Bit 14 is Read/Write Clear. All other bits are ...
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Register Description 3.7.5 RID – Revision Identification (Device #0) Address Offset: Default Value: Access: Size: This register contains the revision number of the GMCH/MCH Device #0. These bits are read only and writes to this register have no effect. Bit ...
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R 3.7.7 BCC – Base Class Code Register (Device #0) Address Offset: Default Value: Access: Size: This register contains the Base Class code of the GMCH/MCH Device #0. This code is 06h indicating a Bridge device. Bit 7:0 Base Class ...
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Register Description 3.7.9 APBASE – Aperture Base Configuration (Device #0) Address Offset: Default Value: Access: Size: The APBASE is a standard PCI Base Address register that is used to set the base of the Graphics Aperture. The standard PCI Configuration ...
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R 3.7.10 SVID – Subsystem Vendor Identification Register (Device #0) Address Offset: Default Value: Access: Size: This value is used to identify the vendor of the subsystem. Bit 15:0 Subsystem Vendor ID (SUBVID): This field should be programmed during boot-up ...
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Register Description 3.7.13 CAPID Capability Identification Register (Device #0) Address Offset: Default: Access: Size The Capability Identification Register uniquely identifies chipset capabilities as defined in the table below. The bits in this register are intended to define a capability ceiling ...
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R 3.7.14 RRBAR – Register Range Base Address Register (Device #0) Address Offset: Default Value: Access: Size: This register requests a 64-kB allocation for the Device registers. The base address is defined by bits and can be ...
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Register Description 3.7.15 GMC – GMCH Miscellaneous Control Register (Device #0) Address Offset: Default Value: Access: Size: Bit 15:10 Reserved 9 Aperture Access Global Enable—R/W. This bit is used to prevent access to the aperture from any port (CPU, PCI0 ...
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R 3.7.16 GGC – GMCH Graphics Control Register (Device 0) Address Offset: Default Value: Access: Size: Bit 15:7 Reserved 6:4 Graphics Mode Select (GMS): This field is used to select the amount of main system memory that is pre-allocated to ...
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Register Description 3.7.17 DAFC – Device and Function Control Register (Device 0) Address Offset: Default Value: Access: Size: This 16-bit register controls the visibility of devices and functions within the GMCH/MCH to configuration software. Bit 15:8 Reserved 7 Device #2 ...
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R 3.7.18 FDHC – Fixed DRAM Hole Control Register (Device #0) Address Offset: Default Value: Access: Size: This 8-bit register controls a single fixed DDR SDRAM hole: 15–16 MB. Bit 7 Hole Enable (HEN): This field enables a memory hole ...
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Register Description Table 30. Attribute Bit Assignment Bits [7, 3] Bits [6, 2] Reserved Reserved example, consider a BIOS that is implemented on the Expansion bus. During the initialization process, ...
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R Figure 6. PAM Registers Reserved Reserved Write Enable (R/W) 1=Enable 0=Disable ® Intel 852GME Chipset GMCH & Intel PAM6 PAM5 PAM4 PAM3 PAM2 PAM1 PAM0 Read ...
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Register Description Table 31. PAM Registers and Associated System Memory Segments PAM Reg PAM0[3:0] Reserved PAM0[7:4] R PAM1[3:0] R PAM1[7:4] R PAM2[3:0] R PAM2[7:4] R PAM3[3:0] R PAM3[7:4] R PAM4[3:0] R PAM4[7:4] R PAM5[3:0] R PAM5[7:4] R PAM6[3:0] R PAM6[7:4] ...
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R Video Buffer Area (A0000h–BFFFFh) Attribute Bits do not control this 128-kB area. The Host-initiated cycles in this region are always forwarded to either PCI0 or PCI2 unless this range is accessed in SMM mode. Routing of accesses is controlled ...
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Register Description 3.7.20 SMRAM – System Management RAM Control Register (Device #0) Address Offset: Default Value: Access: Size: The SMRAM register controls how accesses to Compatible and Extended SMRAM spaces are treated. The Open, Close, and Lock Bits function only ...
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R 3.7.21 ESMRAMC – Extended System Management RAM Control (Device #0) Address Offset: Default Value: Access: Size: The Extended SMRAM register controls the configuration of Extended SMRAM Space. The Extended SMRAM (E_SMRAM) Memory provides a Write-Back cacheable SMRAM Memory Space ...
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Register Description 3.7.22 ERRSTS – Error Status Register (Device #0) Address Offset: Default Value: Access: Size: This register is used to report various error conditions. An SERR or SMI cycle may be generated on a zero to one transition of ...
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R 3.7.23 ERRCMD – Error Command Register (Device #0) Address Offset: Default Value: Access: Size: This register enables various errors to generate. The actual generation of the SERR message is globally enabled for Device #0 via the PCI Command register. ...
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Register Description Bit 4:2 Reserved 1 SERR on Multiple-bit ECC Error For systems that support ECC, this field must be set Reserved 0 SERR on Single-bit ECC Error For systems that support ...
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R 3.7.25 SCICMD – SCI Error Command Register (Device #0) Address Offset: Default Value: Access: Size: This register enables various errors to generate a SCI cycle. When an Error Flag is set in the ERRSTS register, it can generate a ...
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Register Description 3.7.26 SHIC - Secondary Host Interface Control Register (Device #0) Address Offset: Default Value: Access: Size: Bit 31:2 Reserved AGP/DVO Mux Strap (Read only): 1 Specifies the use of AGP bus muxed with DVO. This bit is defined ...
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R 3.7.28 AGPSTAT – AGP Status Register (Device #0) Address Offset: Default Value: Access: Size: This register reports AGP device capability/status. Bit 31:24 Request (RQ). Indicates a maximum of 32 outstanding AGP command requests can be handled by the GMCH/MCH. ...
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Register Description 3.7.29 AGPCMD – AGP Command Register (Device #0) Address Offset: Default Value: Access: Size: This register provides control of the AGP operational parameters. Bit 31:10 Reserved 9 Side Band Addressing Enable (SBA_EN). When this bit is set to ...
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R 3.7.30 AGPCTRL – AGP Control Register (Device #0) Address Offset: Default Value: Access: Size: This register provides for additional control of the AGP interface. Note: Bit 7 is visible to the operating system and must be retained in this ...
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Register Description 3.7.32 APSIZE – Aperture Size (Device #0) Address Offset: Default Value: Access: Size: This register determines the effective size of the Graphics Aperture used for a particular GMCH/MCH configuration. This register can be updated by the GMCH/MCH-specific BIOS ...
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R 3.7.33 ATTBASE – Aperture Translation Table Base Register (Device #0) Address Offset: Default Value: Access: Size: This register provides the starting address of the Graphics Aperture Translation Table Base located in the main DDR SDRAM. This value is used ...
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Register Description 3.7.34 AMTT – AGP Interface Multi-Transaction Timer Register (Device #0) Address Offset: Default Value: Access: Size: AMTT is an 8-bit register that controls the amount of time that the GMCH/MCH’s arbiter allows AGP/PCI master to perform multiple back-to-back ...
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R 3.7.35 LPTT – Low Priority Transaction Timer Register (Device #0) Address Offset: Default Value: Access: Size: LPTT is an 8-bit register similar in a function to AMTT. This register is used to control the minimum tenure on the AGP ...
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Register Description 3.8 Main Memory Control, Memory I/O Control Registers (Device #0, Function #1) The following table shows the GMCH/MCH Configuration Space for Device #0, Function #1. Table 32. Host-Hub interface Bridge/System Memory Controller Configuration Space (Device #0, Function#1) Register ...
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R 3.8.1 VID – Vendor Identification Register (Device #0,Function #1) Address Offset: Default Value: Access: Size: The VID register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identifies any PCI device. Writes to ...
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Register Description 3.8.3 PCICMD – PCI Command Register (Device #0,Function #1) Address Offset: Default Value: Access: Size: Since GMCH/MCH Device #0 does not physically reside on PCI_A, many of the bits are not implemented. Bit 15:10 Reserved 9 Fast Back-to-Back ...
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R 3.8.4 PCISTS – PCI Status Register (Device #0,Function #1) Address Offset: Default Value: Access: Size: PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0’s PCI Interface. Bit 14 is Read/Write Clear. All ...
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Register Description 3.8.5 RID – Revision Identification Register (Device #0,Function #1) Address Offset: Default Value: Access: Size: This register contains the revision number of the GMCH/MCH Device #0. These bits are Read Only and Writes to this register have no ...
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R 3.8.8 HDR – Header Type Register (Device #0,Function #1) Address Offset: Default Value: Access: Size: This register identifies the header layout of the configuration space. No physical register exists at this location. Bit 7:0 PCI Header (HDR): This field ...
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Register Description 3.8.11 CAPPTR – Capabilities Pointer Register (Device #0,Function #1) Address Offset: Default Value: Access: Size: The CAPPTR provides the offset that is the pointer to the location of the first device capability in the capability list. Bit 7:0 ...
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R 3.8.13 DRA – DRAM Row Attribute Register (Device #0,Function #1) Address Offset: Default Value: Access: Size: The DDR SDRAM Row Attribute register defines the page sizes to be used when accessing different pairs of rows. Each nibble of information ...
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Register Description 3.8.14 DRT – DRAM Timing Register (Device #0,Function #1) Address Offset: Default Value: Access: Size: This register controls the timing of the DDR SDRAM controller. Bit 31 DDR Internal Write to Read Command delay (tWTR): The tWTR is ...
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R Bit 27:26 Back To Back Read-Write commands spacing (DDR, same or different Rows/Bank): This field determines the RD-WR command spacing, in terms of common clocks based on the following formula 0.5xBL + TA (RD-WR) – DQSS DQSS: ...
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Register Description Bit 14:12 Refresh Cycle Time (tRFC): Refresh Cycle Time is measured for a given row from REF command (to perform a refresh) until following ACT to same row (to perform a Read or Write tracked separately ...
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R Bit 3:2 DDR SDRAM RAS# to CAS# Delay (tRCD): This bit controls the number of clocks inserted between a Row Activate command and a Read or Write command to that row. Encoding 00: 01: 10: 11: 1:0 DDR SDRAM ...
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Register Description 3.8.15 PWRMG – DRAM Controller Power Management Control Register (Device #0,Function #1) Address Offset: Default Value: Access: Size: Bit 31:24 Reserved 23:20 Row State Control: This field determines the number of clocks the system memory controller will remain ...
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R Bit 12 Dynamic Memory Interface Power Management Dynamic Memory Interface Power Management Enabled Dynamic Memory Interface Power Management Disabled. 11 Rcven DLL shutdown disable Normal operation. RCVEN DLL is turned off when the ...
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Register Description 3.8.16 DRC – DRAM Controller Mode Register (Device #0,Function #1) Address Offset: Default Value: Access: Size: Bit 31:30 Revision Number (REV): Reflects the revision number of the format used for DDR SDRAM register definition (Read Only). 29 Initialization ...
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R Bit 9:7 Refresh Mode Select (RMS): This field determines whether Refresh is enabled and, if so, at what rate Refreshes will be executed. Refresh disabled 000: Refresh enabled. Refresh interval 15.6 µsec 001: Refresh enabled. Refresh interval 7.8 µsec ...
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Register Description Bit 6:4 Mode Select (SMS). These bits select the special operational mode of the DDR SDRAM Interface. The special modes are intended for initialization at power up. 000: Post Reset State – When the GMCH exits Reset (power-up ...
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R Bit 3 Reserved 2 DDR SDRAM Burst Length: This bit is used to select the DDR SDRAM controller’s Burst Length operation mode. It must be set consistently to the DDR SDRAM component setting. Can be set ...
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Register Description 3.8.17 DTC – DRAM Throttling Control Register (Device #0,Function #1) Offset Address: Default Value: Access: Size: Throttling is independent for system memory banks, GMCH Writes, and Thermal Sensor Trips. Read and Write Bandwidth is measured independently for each ...
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R Bit 0111 = SDRAM Throttling begins based on the setting in RTTC. 1000 = field is reached, DDR SDRAM Throttling begins based on the setting in RCTC. 1001 = throttling are both enabled. If GMCH Thermal Sensor is tripped, ...
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Register Description Bit 23:20 Write Counter Based Power Throttle Control (WCTC): These bits select the counter based Power Throttle Bandwidth Limits for Write operations to system memory. R/ Throttle Lock ...
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R Bit 15:12 Write Thermal Based Power Throttle Control (WTTC): These bits select the Thermal based Power Throttle Bandwidth Limits for Write operations to system memory. R/ Throttle Lock 65% ...
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Register Description 3.9 Configuration Process Registers (Device #0, Function #3) Table 33 summarizes all Device#0, Function #3 registers. Table 33. Configuration Process Configuration Space (Device#0, Function #3) Register Register Name Symbol Vendor VID Identification Device DID Identification PCI PCICMD Command ...
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R 3.9.1 VID – Vendor Identification Register (Device #0) Address Offset: Default Value: Access: Size: The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification register uniquely identifies any PCI device. Writes to this ...
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Register Description 3.9.3 PCICMD – PCI Command Register (Device #0) Address Offset: Default Value: Access: Size: Since GMCH/MCH Device #0 does not physically reside on PCI_A, many of the bits are not implemented. Bit 15:10 Reserved 9 Fast Back-to-Back Enable ...
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R 3.9.4 PCISTS – PCI Status Register (Device #0) Address Offset: Default Value: Access: Size: PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0’s PCI Interface. Bit 14 is Read/Write clear. All other ...
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Register Description 3.9.5 RID – Revision Identification Register (Device #0) Address Offset: Default Value: Access: Size: This register contains the revision number of the GMCH/MCH. These bits are Read Only; Writes to this register have no effect. Bit 7:0 Revision ...
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R 3.9.8 HDR – Header Type Register (Device #0) Address Offset: Default Value: Access: Size: This register identifies the header layout of the configuration space. No physical register exists at this location. Bit 7:0 PCI Header (HDR): This field always ...
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Register Description 3.9.11 CAPPTR – Capabilities Pointer Register (Device #0) Address Offset: Default Value: Access: Size: The CAPPTR provides the offset that is the pointer to the location of the first device capability in the capability list. Bit 7:0 Pointer ...
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R 3.9.13 HPLLCC – HPLL Clock Control Register (Device #0) Address Offset: Default Value: Access: Size: Bit 15:11 Reserved 10 HPLL VCO Change Sequence Initiate Bit: Software must Write clear this bit and then Write a 1 ...
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Register Description 3.10 PCI to AGP Configuration Registers (Device #1, Function #0) Table 35. Device 1 is the Virtual PCI to AGP bridge (Device #1, Function #0)) Register Name Vendor Identification Device Identification PCI Command Register PCI Status Register Revision ...
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R Register Name Bridge Control Register Error Command Register 3.10.1 VID1 - Vendor Identification (Device #1) Address Offset: Default Value: Access: Size: The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely ...
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Register Description 3.10.3 PCICMD1 - PCI Command Register (Device #1) Address Offset: Default Value: Access: Size: Bit 15:9 Reserved 8 SERR Message Enable (SERRE): This bit is a global enable bit for Device #1 SERR messaging. The GMCH/MCH communicates the ...
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R 3.10.4 PCISTS1 - PCI Status Register (Device #1) Address Offset: Default Value: Access: Size: PCISTS1 is a 16-bit status register that reports the occurrence of error conditions associated with the primary side of the “virtual” PCI to PCI bridge ...
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Register Description 3.10.6 SUBC1 - Sub-Class Code (Device #1) Address Offset: Default Value: Access: Size: This register contains the Sub-Class Code for the GMCH/MCH Device #1. This code is 04h indicating a PCI to PCI Bridge device. Bit 7:0 Sub-Class ...
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R 3.10.9 PBUSN1 - Primary Bus Number (Device #1) Address Offset: Default Value: Access: Size: This register identifies that “virtual” PCI to PCI bridge is connected to bus #0. Bit 7:0 Primary Bus Number (BUSN): Configuration software typically programs this ...
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Register Description 3.10.11 SUBUSN1 - Subordinate Bus Number (Device #1) Address Offset: Default Value: Access: Size: This register identifies the subordinate bus (if any) that resides at the level below PCI_B/AGP. This number is programmed by the PCI configuration software ...
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R 3.10.13 IOBASE1 - I/O Base Address Register (Device #1) Address Offset: Default Value: Access: Size: This register controls the CPU to PCI_B/AGP I/O access routing based on the following formula: IO_BASE=< address =<IO_LIMIT Only upper 4 bits are programmable. ...
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Register Description 3.10.15 SSTS1 - Secondary Status Register (Device #1) Address Offset: Default Value: Access: Size: SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with a secondary side (i.e. PCI_B/AGP side) of the “virtual” ...
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R 3.10.16 MBASE1 - Memory Base Address Register (Device #1) Address Offset: Default Value: Access: Size: This register controls the CPU to PCI_B non-prefetchable memory access routing based on the following formula: MEMORY_BASE=< address =<MEMORY_LIMIT The upper 12 bits of ...
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Register Description 3.10.17 MLIMIT1 - Memory Limit Address Register (Device #1) Address Offset: Default Value: Access: Size: This register controls the CPU to PCI_B non-prefetchable memory access routing based on the following formula: MEMORY_BASE=< address =<MEMORY_LIMIT The upper 12 bits ...
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R 3.10.18 PMBASE1 - Prefetchable Memory Base Address Reg (Device #1) Address Offset: Default Value: Access: Size: This register controls the CPU to PCI_B prefetchable memory accesses routing based on the following formula: PREFETCHABLE_MEMORY_BASE=< address =<PREFETCHABLE_MEMORY_LIMIT The upper 12 bits ...
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Register Description 3.10.19 PMLIMIT1 - Prefetchable Memory Limit Address Reg (Device #1) Address Offset: Default Value: Access: Size: This register controls the CPU to PCI_B prefetchable memory accesses routing based on the following formula: PREFETCHABLE_MEMORY_BASE=< address =<PREFETCHABLE_MEMORY_LIMIT The upper 12 ...
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R 3.10.20 BCTRL - Bridge Control Register (Device #1) Address Offset: Default Value: Access: Size: This register provides extensions to the PCICMD1 register that are specific to PCI to PCI bridges. The BCTRL provides additional control for the secondary interface ...
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Register Description Bit ISA Enable (ISAEN): Modifies the response by the GMCH/MCH to an I/O access 2 issued by the CPU that target ISA I/O addresses. This applies only to I/O addresses that are enabled by the IOBASE and IOLIMIT ...
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R 3.11 Intel 852GME GMCH Integrated Graphics Device Registers (Device #2, Function #0) This section contains the PCI configuration registers listed in order of ascending offset address. Device #2 incorporates Function #0. Note: C0F0 = Copy of Function #0 and ...
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Register Description Register Name Power Management Capabilities Power Management Control SWSMI Register Thermal INTR Command Register GMCH Clock Control Register 3.11.1 VID – Vendor Identification Register (Device #2) Address Offset: Default Value: Access Attributes: Size: The VID register contains the ...
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R 3.11.3 PCICMD – PCI Command Register (Device #2) Address Offset: Default: Access: Size: This 16-bit register provides basic control over the IGD’s ability to respond to PCI cycles. The PCICMD register in the IGD disables the IGD PCI compliant ...
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Register Description 3.11.4 PCISTS – PCI Status Register (Device #2) Address Offset: Default Value: Access: Size: PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and PCI compliant target abort. PCISTS also indicates ...
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R 3.11.6 CC – Class Code Register (Device #2) Address Offset: Default Value: Access: Size: This register contains the device programming interface information related to the Sub-Class code and Base Class code definition for the IGD. This register also contains ...
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Register Description 3.11.9 HDR – Header Type Register (Device #2) Address Offset: Default Value: Access: Size: This register contains the Header Type of the IGD. Bit 7 Multi Function Status (MFunc): Indicates if the device is a multi-function device. 6:0 ...
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R 3.11.11 MMADR – Memory Mapped Range Address Register (Device #2) Address Offset: Default Value: Access: Size: This register requests allocation for the IGD registers and instruction ports. The allocation is for 512-kB and the base address is defined by ...
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Register Description 3.11.13 SVID – Subsystem Vendor Identification Register (Device #2) Address Offset: Default Value: Access: Size: Bit 15:0 Subsystem Vendor ID: This value is used to identify the vendor of the subsystem. This register should be programmed by BIOS ...
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R 3.11.16 INTRLINE Interrupt Line Register (Device #2) Address Offset: Default Value: Access: Size: Bit 7:0 Interrupt Connection: Used to communicate interrupt line routing information. POST software Writes the routing information into this register as it initializes and configures the ...
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Register Description 3.11.19 MAXLAT – Maximum Latency Register (Device #2) Address Offset: Default Value: Access: Size: Bit 7:0 Maximum Latency Value: Bits[7:0]=00h. The IGD has no specific requirements for how often it needs to access the PCI bus. 3.11.20 PMCAP ...
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R 3.11.21 PMCS – Power Management Control/Status Register (Device #2) Address Offset: Default Value: Access: Size: Bit 15 PME_Status from D3 (cold). 14:9 Reserved 8 PME_En RO: This bit indicate that PME# assertion from D3 (cold) is ...
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Register Description 3.11.22 GCCC GMCH Clock Control Register Address Offset: Default Value: Access: Size: Bit 15:10 Reserved 9 Core Display Clock Gate Control (CD-Gate Core Display Clock Trunk not Gated, Clock running to the Core Core ...
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R 4 System Address Map A system based on the GMCH/MCH supports addressable system memory space and 64- kB addressable I/O space. The I/O and system memory spaces are divided by system configuration software into ...
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System Address Map Figure 7. Simplified View of Intel 852GME GMCH and Intel 852PM MCH System Address Map 4GB Top of the M ain M emory 0 162 Intel PCI M emory Graphic AGP Address Address Range ( Local) Range ...
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R Figure 8. Detailed View of the Intel 852GME GMCH and Intel 852PM MCH System Address Map 4.2 DOS* Compatibility Area This compatibility region is divided into the following address regions: Source synchronous 0 - 640 kB DOS Area 640 ...
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System Address Map Table 37. System Memory Segments and Their Attributes System Memory Segments 000000H - 09FFFFH 0A0000H - 0BFFFFH 0C0000H - 0C3FFFH 0C4000H - 0C7FFFH 0C8000H - 0CBFFFH 0CC000H - 0CFFFFH 0D0000H - 0D3FFFH 0D4000H - 0D7FFFH 0D8000H - ...
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R IGD is not enabled. AGP cycles are allowed to master abort and hub interface writes are forwarded to AGP; hub interface reads are handled as invalid cycles. If IGD is enabled, all hub interface accesses are handled as invalid ...
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System Address Map 4.4 Main System Memory Address Range (0010_0000h to Top of Main Memory) The address range from 1-MB to the top of main system memory is mapped to main DDR SDRAM address range controlled by the GMCH/MCH. The ...
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R 4.4.2.1 Extended SMRAM Address Range (HSEG and TSEG) The HSEG and TSEG SMM transaction address spaces reside in this extended system memory area. 4.4.2.2 HSEG SMM mode processor accesses to enabled HSEG are remapped to 000A0000h-000BFFFFh. Non- SMM mode ...
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System Address Map 1. The first exception is addresses decoded to the Graphics Memory range. One per function in device #2. 2. The second exception is addresses decoded to the system memory mapped range of the Internal Graphics device. One ...
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R 4.4.2.8 AGP Memory Address Ranges The GMCH/MCH can be programmed to direct memory accesses to the AGP bus interface when addresses are within either of two ranges specified via registers in GMCH/MCH’s Device #1 configuration space. The first range ...
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System Address Map 4.4.3 System Management Mode (SMM) Memory Range The GMCH/MCH supports the use of main system memory as System Management RAM (SMM RAM) enabling the use of System Management mode. The GMCH/MCH supports three SMM options: Compatible SMRAM ...
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R address range. Note that the High DDR SDRAM space is the same as the Compatible Transaction Address space. Table 46 describes three unique address ranges: 1. Compatible Transaction Address (Adr C) 2. High Transaction Address (Adr H) 3. TSEG ...
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System Address Map 4.4.4 System Memory Shadowing Any block of system memory that can be designated as Read-Only or Write-Only can be “shadowed” into GMCH/MCH DDR SDRAM. Typically this is done to allow ROM code to execute more rapidly out ...
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R I/O_Base_Address The effective size of the range is programmed by the plug-and-play configuration software and it depends on the size of I/O space claimed by the AGP device. The GMCH/MCH also forwards accesses to the Legacy VGA I/O ranges ...
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System Address Map 4.4.6.1.1 Hub Interface Accesses to GMCH/MCH that Cross Device Boundaries Hub interface accesses are limited to 256-bytes but have no restrictions on crossing address boundaries. A single hub interface request may therefore span device boundaries (AGP, DDR ...
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R Reads: Remap to memory address 0h, return data from address 0h, and set the IAAF error flag. Writes: Re-mapped to memory address 0h with BE’s de-asserted (effectively dropped “on the floor”) and set the IAAF error flag. AGP Accesses ...
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System Address Map 176 Intel This page intentionally left blank. ® 852GME Chipset GMCH & Intel ® 852PM Chipset MCH Datasheet R ...
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R 5 Functional Description 5.1 Host Interface Overview The processor system bus uses source synchronous transfers for the address and data signals. The address signals are double pumped and two addresses can be generated every bus clock. At 100 MHz ...
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Functional Description PCI bus instead of asserting a hardware signal to the IOxAPIC. The MSI may be directed to the IOxAPIC, which in turn generates an interrupt as an upstream hub interface Memory Write. Alternatively the MSI may be directed ...
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R Before any cycles to the system memory interface can be supported, the GMCH/MCH DDR SDRAM registers must be initialized. The GMCH/MCH must be configured for operation with the installed system memory types. Detection of system memory type and size ...
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Functional Description minimize the latency required to initiate and complete requests to system memory, and to support the highest possible bandwidth (full streaming, quick turn-arounds). One measure of performance is the total flight time to complete a cache line request. ...
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R Figure 9. Intel 852GME GMCH Graphics Block Diagram AGP2.0 Instr./ Data High bandwidth access to data is provided through the system memory port. The GMCH accesses UMA memory located in system memory at 1.06 GB/s. The GMCH uses a ...
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Functional Description Gouraud shading Alpha-blending Per-Vertex and Per- Pixel fog Z/W buffering These features are independently controlled via a set of 3D instructions. The 3D pipeline subsystem performs the 3D rendering acceleration. The main blocks of the pipeline are the ...
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R 5.4.2.5 Backface Culling As part of the setup, the GMCH can discard polygons from further processing, if they are either facing away from or towards the user’s viewpoint. This operation, referred to as “Back Face Culling” is accomplished based ...
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Functional Description makes those portions of the object transparent (the previous contents of the back buffer show through). For “linear“ texture filtering modes, the texture filter is modified if only the non-nearest neighbor texels match the key (range). Chromakeying can ...
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R desired pixel are selected. The Final texture value is generated by linear interpolation between the two texels selected from each of the MIP Maps. Linear MIP Linear (Trilinear MIP Mapping): This is used if many LODs are present. Two ...
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Functional Description corresponding components resulting from the Texture Engine. These textured pixels are modified by the specular and fog parameters. These specular highlighted, fogged, textured pixels are color blended with the existing values in the frame buffer. In parallel, stencil, ...
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R 5.4.3.5 Vertex and Per Pixel Fogging Fogging is used to create atmospheric effects such as low visibility conditions in flight simulator- type games. It adds another level of realism to computer-generated scenes. Fog can be used for depth cueing ...
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Functional Description 5.4.3.8 Depth Buffer The Raster Engine is able to read and write from this buffer and use the data in per fragment operations that determine resultant color and depth value of the pixel for the fragment are to ...
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R 5.4.4.1 256-Bit Pattern Fill and BLT Engine Use of this BLT engine accelerates the Graphical User Interface (GUI) of Microsoft Windows*. The GMCH BLT Engine provides hardware acceleration of block transfers of pixel data for many common Windows operations. ...
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Functional Description 5.4.5.1 Dual Pipe Independent Display Functionality The display consists of two display pipes, A and B. Pipes have a set of planes that are assigned to them as sources. The analog display port may only use Pipe A ...
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R 5.4.7 Overlay Plane The overlay engine provides a method of merging either video capture data (from an external Video Capture device) or data delivered by the processor, with the graphics data on the screen. 5.4.7.1 Multiple Overlays (Display C) ...
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Functional Description in the scene. Vertical filtering or “Bob” interpolates adjacent lines rather replicating the nearest neighbor. This is the best solution for images with motion however, it will have reduced spatial resolution in areas that have no motion and ...
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R The GMCH supports sub-picture for DVD and DBS by mixing the two video streams via alpha blending. Unlike color keying, alpha blending provides a softer effect and each pixel that is displayed is a composite between the two video ...
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Functional Description corruption of the values. From that point on, the display modes are changed by selecting a different source size for that pipe, programming the VGA registers, or selecting a source size and enabling the VGA. The timing signals ...
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R pairs of which eight are data and two are clocks. The phase locked transmit clock is transmitted in parallel with the data being sent out over the data pairs and over the LVDS clock pair. Each channel supports transmit ...
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Functional Description 5.5.2.4 LVDS Pair States The LVDS pairs can be put into one of five states: powered down tri-state, powered down Zero Volts, common mode, send zeros, or active. When in the active state, several data formats are supported. ...
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R 5.5.2.9.1 Panel Power Sequence States A defined power sequence is recommended when enabling the panel or disabling the panel. The set of timing parameters can vary from panel to panel vendor, provided that they stay within a predefined range ...
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Functional Description Table 43. Display Configuration Space Name T1+T2 Vdd On to LVDS Active Panel Vdd must be on for a minimum time before the LVDS data stream is enabled. T5 Backlight LVDS data must be enabled for a minimum ...
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R The digital display port consists of a digital data bus, VSYNC, HSYNC, and BLANK# signals. The data bus can operate in a 12-bit or 24-bit mode. Embedded sync information or HSYNC and VSYNC signals can optionally provide the basic ...
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Functional Description AGP C/BE[3:0]# Command Encoding 0100 Hi-Priority 0101 Write 0101 Reserved 0110 Reserved 0111 Long Read 1000 Hi-Priority 1001 Long Read Flush 1010 Reserved 1011 Fence 1100 Reserved 1101 Reserved 1110 Reserved 1111 NOTE: N/A refers to a function ...