82555 Intel Corporation, 82555 Datasheet
82555
Specifications of 82555
Related parts for 82555
82555 Summary of contents
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... Mbps LAN Physical Layer Interface Networking Silicon Product Features Optimal integration for lower cost solutions — Integrated 10/100 Mbps single chip physical layer interface solution — Complete 10/100 Mbps MII compliance with MDI support — Full duplex operation in 10 Mbps and 100 Mbps modes — ...
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... The 82555 10/100 Mbps LAN Physical Layer Interface may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. ...
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... Adapter Mode Addresses ..............................................................................................19 5.0 10BASE-T FUNCTIONALITY IN ADAPTER MODE ..................................................................21 5.1 10BASE-T Transmit Clock Generation..........................................................................21 5.2 10BASE-T Transmit Blocks ...........................................................................................21 5.2.1 10BASE-T Manchester Encoder................................................................21 5.2.2 10BASE-T Driver and Filter .......................................................................21 5.3 10BASE-T Receive Blocks ............................................................................................21 5.3.1 10BASE-T Manchester Decoder................................................................21 5.3.2 10BASE-T Twisted Pair Ethernet (TPE) Receive Buffer and Filter............21 Datasheet Networking Silicon — 82555 Contents iii ...
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... Transmit Packet Timing Parameters ......................................................... 48 11.4.5 Squelch Test Timing Parameters .............................................................. 48 11.4.6 Jabber Timing Parameters ........................................................................ 49 11.4.7 Receive Packet Timing Parameters .......................................................... 49 11.4.8 10BASE-T Normal Link Pulse (NLP) Timing Parameters ......................... 50 11.4.9 Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters .................... 50 11.4.10 Reset Timing Parameters ......................................................................... 51 11.4.11 X1 Clock Specifications ............................................................................ 51 11.4.12 100BASE-TX Transmitter AC Specification .............................................. 52 12.0 82555 PACKAGE INFORMATION............................................................................................. 53 iv Datasheet ...
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... When configured to DTE (adapter) mode, the 82555 incorporates all active circuitry required to interface 10/100 Mbps Ethernet controllers and CSMA/CD MAC components to 10 Mbps and 100 Mbps networks. In this and other documents the 82555 may be referred to as the DTE, Physical Medium Device (PMD), or Physical Layer Medium (PLM). It supports a direct glueless interface to Intel components such as the 82557 Fast Ethernet controller ...
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... Networking Silicon The 82555 also complies with the IEEE 802.3u Auto-Negotiation and the IEEE 802.3x Full Duplex Flow Control sections. The MAC interface on the 82555 is a superset of the IEEE 802.3u Media Independent Interface (MII) standard. 2 Datasheet ...
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... Architectural Overview The 82555 is an advanced combination of both digital and analog logic which combine to provide a functional stack between the Media Independent Interface (MII) and the wire through the magnetics. Figure 2 2.1 100 Mbps Mode In 100BASE-TX mode the 82555 digital subsection performs all signal processing of digital data obtained from the analog reception and the data to be driven into the analog transmit subsection ...
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... Mbps stream, recovering both clock and data signals. MII TX Interface 2.2 10 Mbps Mode The 82555 operation in 10BASE-T mode is similar to the 82555 operation in 100BASE-TX mode. Manchester encoding and decoding is used instead of 4B/5B encoding/decoding and scrambling/ descrambling. In addition, the Transmit Clock and Receive Clock (MII clock signals) provide 2.5 MHz instead of 25 MHz. ...
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... The 82555 provides a glueless interface to Intel components such as the 82557 Fast Ethernet Controller, as well as any MII compatible device. 82557 Fast Ethernet controller implementation connected to the 82555 using the MII interface. Flash (optional) 2.3 Media Independent Interface (MII) The 82555 supports the Media Independent Interface (MII) as its primary interface to the MAC. ...
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... Networking Silicon Signal Name Transmit Error TXERR (repeater mode only) 6 Table 1. 82555 MII Description Direction From RIC Clock MII Signal Supported Reference by the 82555? TXC Yes Datasheet ...
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... All active digital pins are defined to have transistor-to-transistor logic voltage levels except the X1 and X2 crystal signals. The transmit differential and receive differential pins are specified as analog outputs and inputs, respectively. The figure below show the pin locations on the 82555 component. The following subsections describe the pin functions. Datasheet Networking Silicon — ...
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... O This type of pin is an output pin from the 82555. I/O This type of pin is both an input and output pin for the 82555. B This pin is used as a bias pin. The bias pin is either pulled up or down with a resistor. The bias pin may also be used as an external voltage reference. ...
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... CRS is an asynchronous output signal. O Collision Detect. The Collision Detect signal operates in half duplex mode and indicates to the 82555 that a collision has occurred on the link. COL is an asynchronous output signal to the controller. I/O Management Data Input/Output. The MDIO signal is a bidirectional data pin for the Management Data Interface (MDI) ...
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... LED driver and will be an active low for all technologies. In repeater mode, this signal is used for Auto-Negotiation advertisement to the 82555’s link partner and activates the PHY Base (Bay Technologies) flow control if 100BASE-TX full duplex is the highest common technology between the 82555 and its link partner ...
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... Datasheet Type Name and Function I Reset. The Reset signal is active high and resets the 82555. A reset pulse width of at least 1 s should be used. I This pin is multiplexed and can be used for one of the following: Force 100/10 Mbps. In repeater mode, this pin configures the repeater to either 100 Mbps (active high Mbps (active low) ...
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... Networking Silicon 3.9 Power and Ground Pins Symbol VCC 7, 9, 15, 17, 19, 27, 29, 31, 36, 38, 40, 45, 58, 62, 64, 66, 73, 75, 83, 88, 93, 98 VSS 3, 8, 10, 14, 16, 18, 20, 26, 28, 30, 32, 35, 37, 39, 41, 46, 49, 53, 57, 61, 63, 65, 67, 72, 74, 78, 84, 89, 91, 94 Pin Type I Power ± 5% ...
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... Transmit Clock Generation A 25 MHz crystal MHz oscillator is used to drive the 82555’s X1 and X2 pins. The 82555 derives its internal transmit digital clocks from this crystal or oscillator input. The Transmit Clock signal is a derivative of the 25 MHz internal clock. The accuracy of the external crystal or oscillator must be ± ...
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... Data is scrambled in 100BASE-TX in order to reduce electromagnetic emissions during long transmissions of high-frequency data codes. The scrambler logic accepts 5 bits from the 4B/5B encoder block and presents the scrambled data to the MLT-3 encoder. The 82555 implements the 11-bit stream cipher scrambler as adopted by the ANSI XT3T9.5 committee for UTP operation. ...
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... Cyclic Redundancy Check (CRC). When TXEN is asserted, the 82555 accepts data on the MII TXD[3:0] lines, encodes it, and sends it out onto the wire. The 82555 encodes the first byte of the preamble as the “JK” symbol, encodes all other pieces of data according to the 4B/5B lookup table, and adds the “ ...
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... Receive Blocks The receive subsection of the 82555 accepts 100BASE-TX MLT-3 data on the receive differential pair. Due to the advanced digital signal processing design techniques employed, the 82555 will accurately receive valid data from Category 5 (CAT5) UTP and Type 1 STP cable of length well in excess of 100 meters ...
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... TXDV and CRS. 4.3.5 100BASE-TX Receive Error Detection and Reporting In 100BASE-TX mode, the 82555 can detect errors in receive data in a number of ways. Any of the following conditions is considered an error: • ...
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... The Auto-Negotiation function is available in both the 82555 and a PHY-T4. For these PHYs to operate together, some arbitration at the PMA level is required and the Auto-Negotiation function of one of the PHYs must be disabled. For this purpose, the 82555 is defined as the master; and the PHY-T4, the slave. In combination mode, only the 82555’s Auto-Negotiation function is enabled (the PHY-T4’ ...
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... Adapter Mode Addresses In DTE (adapter) mode, the 82555 supports addresses and 3 through the pins PHYA1 and PHYA0. Four addresses are sufficient in the case of a combination adapter having three PHYs. For switch applications, the T4ADV signal should be de-asserted to allow all 32 addresses to be available in repeater mode ...
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... Networking Silicon 20 Datasheet ...
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... Functionality in Adapter Mode 5.1 10BASE-T Transmit Clock Generation The 20 MHz and 10 MHz clocks needed for 10BASE-T are synthesized from the external 25 MHz crystal or oscillator. The 82555 provides the transmit clock and receive clock to the MAC at 2.5 MHz. 5.2 10BASE-T Transmit Blocks 5.2.1 10BASE-T Manchester Encoder After the 2 ...
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... The link integrity in 10 Mbps works with link pulses. The 82555 senses and differentiates those link pulses from fast link pulses and from 100BASE-TX idles. In the first and last case, the 82555 activates parallel detection of the respective technology; and in the second case, Auto-Negotiation. ...
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... Full Duplex The 82555 supports 10 Mbps full duplex by disabling the collision function, the squelch test, and the carrier sense transmit function. This allows the 82555 to transmit and receive simultaneously, achieving Mbps of network bandwidth. The configuration can be achieved through Auto- Negotiation ...
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... Networking Silicon 24 Datasheet ...
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... Connectivity A 25 MHz buffered oscillator can provide the clock to all of the 82555 devices. A 2.5 MHz (10 Mbps MHz (100 Mbps) signal is required to clock the RIC and the TXC signal in the PHYs. TXD[3:0], TXERR, RXC, RXD[3:0], RXDV, and RXERR are single-bus (shortened) for all Datasheet Networking Silicon — ...
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... Networking Silicon PHYs connected to the RIC. Signals TXEN, CRS, and PORTEN are connected from each of the 82555 devices to the specified RIC pin. The figure below illustrates an example of multiple 82555s connected MHz (or 2.5 MHz) oscillator. 26 RIC CLK 2.5/25 MHz (10/100) TXCLK ...
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... MDIO pin. For read cycles, the controller drives the transition bits and data onto the MDIO pin; for write cycles, to the 82555. The controller drives addresses and data on the falling edge of the MDC signal, and the 82555 latches the data on the rising edge of the MDC signal. The following list defines protocol terms: ...
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... Networking Silicon The 82555 address can be configured to four 0 through 3 in DTE (adapter) mode and 0 through 31 in repeater mode. A special functions for switches allows 32 addresses to exist in repeater mode. The management frame structure is as follows: Transition READ WRITE 7.2 MDI Registers MDI registers are described in the following subsections and the acronyms mentioned in the registers are defined as follows Self Cleared ...
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... Restart Auto-Negotiation process 0 = Normal operation This bit controls the duplex mode when Auto-Negotiation is disabled. If the 82555 reports that it is only able to operate in one duplex mode, the value of this bit shall correspond to the mode which the 82555 can operate. When the 82555 is placed in Loopback mode, the behavior of the PHY shall not be affected by the status of this bit, bit 8 ...
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... Technology Ability Field is an 8-bit field containing information indicating supported technologies specific to the selector field value. The Selector Field is a 5-bit field identifying the type of message to be sent via Auto-Negotiation. This field is read only in the 82555 and contains a value of 00001b, IEEE Standard 802.3. Default R/W -- ...
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... Description This bit reflects the 82555’s link partner’s Auto- Negotiation ability. This bit is used to indicate that the 82555 has successfully received its link partner’s Auto- Negotiation advertising ability. This bit reflects the 82555’s link partner’s Auto- Negotiation ability. This bit reflects the 82555’ ...
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... Networking Silicon 7.2.3.1 Register 16: 82555 Status and Control Register Bit Definitions Bit(s) Name 15 Flow Control 14 Reserved 13 Carrier Sense Disconnect Control 12 Transmit Flow Control Disable 11 Receive De- Serializer In-Sync Indication 10 100BASE-TX Power-Down 9 10BASE-T Power-Down 8 Polarity 7:3 Reserved Speed 0 Duplex Mode 7.2.3.2 Register 17: 82555 Special Control Bit Definitions ...
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... This field contains a 16-bit counter that increments once per frame for any receive error condition (such as a symbol error or premature end of frame) in that frame. The counter stops when full (and does not roll over) and self-clears on read. Networking Silicon — 82555 Default R ...
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... End of Frame Counter 7.2.3.8 Register 25: 10BASE-T Transmit Jabber Detect Counter Bit Definitions Bit(s) Name 15:0 Jabber Detect Counter 7.2.3.9 Register 27: 82555 Special Control Bit Definitions Bit(s) Name 15:3 Reserved 2:0 LED Switch Control 34 Description This field contains a 16-bit counter that increments for each symbol error. The counter stops when full (and does not roll over) and self-clears on read ...
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... Half Duplex. Since only one technology can be used at a time (after every renegotiate command), a prioritization scheme must be used to ensure that the highest common denominator ability is chosen. Table 4 set according to what the PHY is capable of supporting. In the case of the 82555, bits and 3 are set. Table 5 lists the priority of each of the technologies. ...
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... This period, known as Force_Fail, insures that the 82555’s link partner has gone into a Link Fail state before Auto-Negotiation or Parallel Detection begins. Thus, both sides (the 82555 and the 82555’s link partner) will perform Auto- 36 Table 5 ...
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... Negotiation or Parallel Detection with no data packets being transmitted. Connection is then established either by FLP exchange or Parallel Detection. The 82555 will look for both FLPs and link integrity pulses. The following diagram illustrates this process. Auto-Negotiation capable = 0 Datasheet Force_Fail Ability detect either by parallel detect or auto- negotiation ...
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... Networking Silicon 38 Datasheet ...
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... Activity: This LED is on (active-low) when activity is detected on the wire. In DTE (adapter) mode, this LED is on during transmit and receive when the 82555 is not in loopback mode. In repeater mode, this LED is on only during receive when the 82555 is not in loopback mode. ...
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... Networking Silicon 40 Datasheet ...
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... Test Port When the TESTEN pin is high, the test pins provide a test access port for the 82555. In test mode, the 82555 will default to address 1. The 82555 has a simple Test Access Port (TAP) from which all the test modes are selected and test instructions are operated. The TAP is controlled by a simple mechanism and handshake. Activation of all test modes requires simple hardware. The TAP signals connected to the 82555 blocks and periphery control the 82555’ ...
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... TCK. The TAP must be reset during power-up. Otherwise, the 82555 can wake-up during high-Z mode or NAND Test, which can be harmful to the board. The TAP should be reset only with a hardware reset input pin and not with software reset. The TOUT control logic selects the TISR output in all tests, except burn-in test modes ...
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... All input voltages -1.0 Parameter Description Min Supply voltage 4.75 Case temperature 0 Condition out out 0 < V < Condition DC and V = RDP (V / Networking Silicon — 82555 Typ Max Units 85 C 140 C 7.0 V 7.0 V 8.0 V 6.0 V Typ Max Units 5. Min Typ Max ...
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... Networking Silicon Symbol Parameter Description V Input differential accept voltage IDA10 V Input differential reject voltage IDR10 V Input common mode voltage ICM10 V Output differential voltage OD10 c I Line driver supply CCT10 d I Current on all V CC10 I Total supply current CCT10TOT e L Leakage on analog pins ILA10 a ...
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... Rbias100 Figure 12. RBIAS100 Resistance versus I Output Levels Figure 13. AC Testing Level Conditions Parameter Conditions 100 Mbps 10 Mbps Networking Silicon — 82555 Min Typ Max Units 235 275 Icct100 CCT100 Input Levels V = 2.0 V ...
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... Networking Silicon 1.5V 11.4.2 MII Timing Parameters Symbol TXD[3:0], TXEN, TXERR setup T7 T TXDV from the rising edge of TXC TXD[3:0], TXEN, TXERR hold T8 T TXH time after the rising edge of TXC RXD[3:0], RXDV, RXERR valid T9 T RXSU before the rising edge of RXC ...
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... Data Valid T13 Data Invalid Data Valid Figure 17. MII Timing Parameters: MDC/MDIO Parameter Conditions a PORTEN T14 RXD[3:0], Signal Driven RXCLK Figure 18. PORT Enable Timing Networking Silicon — 82555 Data Invalid T12 Data Invalid Data Invalid Min Typ Max Units RXC 1.5 2.5 clocks RXC 1 ...
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... Networking Silicon 11.4.4 Transmit Packet Timing Parameters Symbol TXC on first TXEN active to start T15 T XEN_ST of frame TXC on first TXEN active to start T T15a XEN_ST of frame TXC on first TXEN active to T16 T XEN_CRSH rising edge of CRS TXC on first TXEN active to T T16a XEN_CRSH ...
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... Figure 20. Squelch Test Timing Parameters Parameter Conditions 10 Mbps 10 Mbps TXEN T22 Figure 21. Jabber Timing Parameters Parameter Conditions 100 Mbps 10 Mbps 100 Mbps 10 Mbps 100 Mbps Networking Silicon — 82555 T21 Min Typ Max Units 26 ms 410 ms T23 Min Typ Max Units 11 ...
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... Networking Silicon Symbol End of receive frame to falling T T26a R_CRSL edge of CRS End of receive frame to falling T27 T R_RXDVL edge of RXDV End of receive frame to falling T T27a R_RXDVL edge of RXDV Frame On link 11.4.8 10BASE-T Normal Link Pulse (NLP) Timing Parameters Symbol T28 T NLP width ...
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... Clock Pulse Data Pulse T35 T34 Figure 24. Fast Link Pulse Timing Parameters Parameter Conditions Power Up (VCC) T37 RESET Figure 25. Reset Timing Parameters Parameter Conditions ±50 PPM Networking Silicon — 82555 Min Typ Max Units Clock Pulse Min Typ ...
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... Networking Silicon 11.4.12 100BASE-TX Transmitter AC Specification Symbol TDP/TDN differential output peak T40 T JIT jitter 52 4.0V 2.5V 0.4V T39 T38 Figure 26. X1 Clock Specifications Parameter Conditions HLS data T39 Min Typ Max Units 300 700 ps Datasheet ...
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... Package Information This section provides the physical packaging information for the 82555. The 82555 is an 100-pin plastic Quad Flat Pack (QFP) device. Package attributes are provided in are shown in Figure Datasheet 27 Seating Plane Y See Detail A Figure 27. Dimension Diagram for the 82555 QFP Table 7 ...
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... Networking Silicon 54 Table 7. Dimensions for the 82555 QFP Symbol Description T Lead Angle Y Coplanarity Min Norm Max 0 0.10 Datasheet ...