SK70744HE Intel Corporation, SK70744HE Datasheet
SK70744HE
Related parts for SK70744HE
SK70744HE Summary of contents
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... Interlocking Spectra (OPTIS) power spectral density (PSD). The chip set consists of two ICs that provide the HDSL2 modem solution: SK70740HE - Analog Front End (AFE) SK70744HE - Transceiver/Framer The SK70740 AFE is separated into a transmit and receive channel. In the transmit channel, the AFE receives a pulse width modulated data stream from the digital transceiver. Switched capacitor filters shape the transmitted signal to suppress out-of-band noise ...
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... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. ...
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Contents 1.0 Pin Assignments and Signal Descriptions 2.0 General Functional Description 2.1 Overview .............................................................................................................19 2.2 Transceiver-AFE Interfaces.................................................................................20 2.2.1 Data Interface.........................................................................................20 2.2.2 Control Interface.....................................................................................20 2.3 JTAG Interface ....................................................................................................20 3.0 AFE Functional Description 3.1 Upstream and Downstream Spectrums ..............................................................22 3.2 Transmitter ..........................................................................................................23 ...
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SK70740/44 — HDSL2 Modem Chip Set 5.0 Register Definitions 5.1 AFE Registers ..................................................................................................... 47 5.2 Transceiver/Framer Registers............................................................................. 49 5.3 PAM Transceiver Registers ................................................................................ 51 5.3.1 Registers 03h through 09h are Reserved .............................................. 52 5.3.2 Registers 0Fh through 17h are Reserved ...
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Simplified State Transition at Activation ..............................................................40 20 Start-Up Sequence..............................................................................................44 21 System Loopback Options ..................................................................................46 22 RCLK Generation Circuit.....................................................................................66 23 AFE Interface Timing...........................................................................................71 24 AFE Data Interface Relative Timing ....................................................................73 25 AFE Control Interface Relative Timing ................................................................74 26 TDM Interface ...
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SK70740/44 — HDSL2 Modem Chip Set 33 Code Generator 1, CG1, R/W, Address = 81h, Default = DAh ........................... 57 34 Code Generator 2, CG2, R/W, Address = 82h Default = CDh ............................ 57 35 Code Generator 3, CG3, R/W, ...
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HDSL2 Receive Overhead Register 4, HRFHOH4, R, Address = D5h...............68 70 Receive Frame Sync Word (First 8 bits), HRFFSW1, R/W, Address = DDh, Default = 00h.......................................................................................................68 71 Receive Frame Sync Word & Stuff Bits, HRFFSWSB, R/W, Address = DEh, ...
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SK70740/44 — HDSL2 Modem Chip Set Revision History Revision Date 8 Description Datasheet ...
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Figure 1. SK70740/44 Block Diagram SK70744 TRANSCEIVER / FRAMER TFSYNC HDSL2 Tx TCLK Scrambler Framer TSER RFSYNC HDSL2 Rx RCLK Descrambler Framer RSER Registers JTAG Datasheet HDSL2 Modem Chip Set — SK70740/44 DAC<3:0> TC PAM Tomlinson PAM Encoder Filter Processor ...
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SK70740/44 — HDSL2 Modem Chip Set 1.0 Pin Assignments and Signal Descriptions Figure 2. Analog Front End Pin Assignments 64 63 DAC3 1 DAC2 2 DAC1 3 DAC0 4 DGND 5 DVCC 6 TDGND 7 TDVCC 8 ADC5 9 ADC4 ...
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Table 1. SK70740 Analog Front End Signal Descriptions Group Pin Symbol 48 Analog 47 Core 49 50 XTALO 42 41 TRING Line Interface 30 29 RRING Transceiver 11 Data Interface ...
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SK70740/44 — HDSL2 Modem Chip Set Table 1. SK70740 Analog Front End Signal Descriptions (Continued) Group Pin 64 58 JTAG 63 Interface IOVCC1 62 IOVCC2 20 IOGND1 Digital 61 IOGND2 Power Supplies ...
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Table 1. SK70740 Analog Front End Signal Descriptions (Continued) Group Pin Symbol 36 RVCC1 34 RVCC2 32 RVCC3 27 RVCC4 RGND1 35 33 RGND2 31 RGND3 28 RGND4 40 TVCC1 44 TVCC2 54 TVCC3 Analog 56 TVCC4 Power 39 TGND1 ...
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... Identifies the particular silicon “stepping” — refer to the specification update for additional stepping information. Lot # Identifies the batch. FPO # Identifies the Finish Process Order Rev # SK70744HE XX Part # XXXXXX LOT # XXXXXXXX FPO # Definition ...
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Table 2. SK70744 Transceiver/Framer Signal Descriptions Group Pin Symbol 53 RST Misc. 83 RBIAS 2 DAC3 1 DAC2 98 DAC1 97 DAC0 AFE 96 ADC5 Data 95 ADC4 Interface 94 ADC3 93 ADC2 92 ADC1 89 ADC0 Clock 84 REFCLK ...
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SK70740/44 — HDSL2 Modem Chip Set Table 2. SK70744 Transceiver/Framer Signal Descriptions (Continued) Group Pin Symbol 61 AD7 60 AD6 59 AD5 58 AD4 57 AD3 56 AD2 55 AD1 54 AD0 76 INTFEC 77 INTPAM RD, ...
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Table 2. SK70744 Transceiver/Framer Signal Descriptions (Continued) Group Pin Symbol 4 TDI 5 TMS JTAG Interface 3 TDO 6 TCK 7 TRST 8 TEST1 9 TEST2 10 TEST3 21 TEST12 22 TEST13 23 TEST14 24 TEST15 25 TEST16 26 TEST17 ...
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SK70740/44 — HDSL2 Modem Chip Set Table 2. SK70744 Transceiver/Framer Signal Descriptions (Continued) Group Pin Symbol 32 VCC1 49 VCC2 79 VCC3 99 VCC4 31 GND1 50 GND2 80 GND3 100 GND4 15 IOVCC1 Power 40 IOVCC2 66 IOVCC3 91 ...
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General Functional Description 2.1 Overview The SK70740/44 chip set provides frame mapping, transceiver, and line interface functions for single pair HDSL2. The SK70740/44 chip set is a highly flexible modem that can be configured through programmable registers for multiple ...
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SK70740/44 — HDSL2 Modem Chip Set 2.2 Transceiver-AFE Interfaces 2.2.1 Data Interface The PAM Transceiver and the AFE work together to provide the Digital-to-Analog (D/A) conversion. A Delta-Sigma modulator in the Transceiver/Framer over-samples the transmit data and produces a pulse ...
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Figure 5. Transceiver/AFE Control Interface Data Structure REFCLK ACE Read Cycle High RSDI R RSDO MSB first Write Cycle High RSDI R RSDO Datasheet HDSL2 Modem ...
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SK70740/44 — HDSL2 Modem Chip Set 3.0 AFE Functional Description The SK70740 Analog Front End (hereafter referred to as the AFE) provides the line interface for the HDSL2 modem. HDSL2 uses overlapping power spectrums for upstream and downstream transmission on ...
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Figure 6. Transmit Frequency Response 3.2 Transmitter The AFE outputs a PAM-16 signal. Within the Transceiver, a Delta-Sigma modulator produces an over-sampled Pulse Width Modulated (PWM) data stream. The data comes across a 4 bit interface port (DAC<3:0>) and is ...
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SK70740/44 — HDSL2 Modem Chip Set 3.4 Line Interface Since the upstream and downstream spectrums overlap, the input to the receiver consists of both spectrums. A hybrid network at the receiver input provides first order echo cancellation, thereby reducing the ...
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Reference Clock The switched capacitor filters and Delta-Sigma modulator in the AFE operate at a fixed frequency. System timing recovery is done digitally in the Transceiver. For typical H2TU-C and H2TU-R applications, the AFE operates with a 21.500 MHz ...
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SK70740/44 — HDSL2 Modem Chip Set 4.0 Transceiver/Framer Functional Description 4.1 TDM Interface 4.1.1 T1 Transport Operation The SK70744 (hereafter referred to as the Transceiver/Framer) is designed to interface with standard T1 framers. The device maps 1.544 Mbps DS1 payloads ...
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Transmit Frame Mapping The frame mapper receives data from the TDM bus and multiplexes a SYNC word, Cyclic Redundancy Check (CRC) bits, HDSL2 Over Head (HOH) and stuff bits into the HDSL2 frame. The data is scrambled prior to ...
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SK70740/44 — HDSL2 Modem Chip Set The Transceiver/Framer supports ANSI EOC messaging by providing access to the EOC bits through the HTFOH1-HTFOH4 and the HRFOH1-HRFOH4 registers. Management of these bits and the HDLC controller function is left to the system ...
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Figure 11. HDSL2 Frame Format for T1 Payload Stuff Sync BLK1 HOH Word 2 bits 10 2316 Byte Byte Table 3. HDSL2 Frame Structure for T1 Frame Bit # ...
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SK70740/44 — HDSL2 Modem Chip Set Table 4. HDSL2 Overhead Bit to Register Mapping HOH bit# Name 1 fsw1 2 fsw2 3 fsw3 4 fsw4 5 fsw5 6 fsw6 7 fsw7 8 fsw8 9 fsw9 10 fsw10 11 crc1 12 ...
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Table 4. HDSL2 Overhead Bit to Register Mapping (Continued) HOH bit# Name 38 segd 39 eoc17 40 eoc18 41 eoc19 42 eoc20 43 eoc21 44 eoc22 45 eoc23 46 eoc24 47 sb1 48 sb2 49 sb3 50 sb4 4.2.2 Receive ...
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SK70740/44 — HDSL2 Modem Chip Set Figure 12. Receive Framer Block Diagram RCLK FIFO Error RSER Counter 4.3 Frame Synchronization See Figure 13. Frame synchronization may be monitored in the Receive Status register (HRFSR) with the fsevent, fcsync, and fsdet ...
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Figure 13. Frame Synchronization Operation Search for Frame FSW = Perfect ? FSW = Perfect ? FSEVENT = ’1’ (HRFSR Register) * When HRFCR bit 6 is set to ’1’, loss of frame sync is automatically declared when 5 frames ...
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SK70740/44 — HDSL2 Modem Chip Set 4.4 Forward Error Correction (FEC) 4.4.1 FEC Encoder The Transceiver/Framer utilizes Trellis Code Modulation (TCM) to provide over coding gain to the HDSL2 transmission system. In the transmit direction, the HDSL2 ...
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Figure 15. Convolutional Encoder 4.4.2 FEC Decoder In the receive direction, the FEC decoder receives 10 bit soft decision words (R) from the slicer. As shown in Figure 16, the outputs from the decoder ...
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SK70740/44 — HDSL2 Modem Chip Set The PAM Transceiver and AFE work together to provide the D/A function. Data from the transmit filter is first passed through a multistage Delta-Sigma modulator. The modulator runs off the REFCLK input from the ...
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While the Tomlinson precoder and transmit filter adjust for line attenuation and crosstalk, they cannot remove Inter-Symbol-Interference (ISI) due to imperfect channel characteristics. An adaptive Feed Forward Equalizer (FFE) is used to reduce ISI from the received data. The equalizer ...
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SK70740/44 — HDSL2 Modem Chip Set 4.9 Activation The activation state machine is fully programmable through firmware. The line rate data fields for the pre-activation frame are written to program memory and downloaded during configuration. The memory locations can vary ...
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Primary Activation At start-up, the Transceiver/Framer begins an activation sequence to synchronize the loop clocks and bring up the DSP blocks. The transceiver activation time is approximately 15 seconds and varies according to the application. Upon activation of the ...
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SK70740/44 — HDSL2 Modem Chip Set Figure 19. Simplified State Transition at Activation No Signal on the line & ACTREQ=0 H2TU-C: Signal detected on the line & ACTREQ=1 FSTAT=1 SNR > & Frame Synchronization 40 Power On / ...
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Inactive State When the Transceiver/Framer is powered up and/or a RST is applied, the transceiver enters the inactive state. When inactive, the transmitter is turned off, the receiver is ready to detect whether there is a signal on the ...
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SK70740/44 — HDSL2 Modem Chip Set Table 6. Start-up Timers Timer Value (sec.) T ACT T IDLE T SILENT T RESYNC 4.9.9 Activating State Machine Configuration of the transceiver signal processing blocks (transmit PSD, AGC, echo canceler, equalization, and timing ...
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STU-R Scrambler = x • STU-R Descrambler = x 4.10 Activation Frame The Activation Frame is used to trade configuration data and precoder coefficients. The format of the Activation Frame is described in T signaling stage, after the signal ...
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SK70740/44 — HDSL2 Modem Chip Set Figure 20. Start-Up Sequence Exception condition Exception condition Exception State Not converged Receiver converged on T not detected r Exception condition 44 H2TU-C H2TU-R Power-On and Power-On Silent Line A B ...
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Table 7. Activation Frame Format (Optional) Activation Frame Bits, LSB : MSB 1:13 14:35 36:57 58:3951 3952:3973 3874:3994 3995:4015 4016:4017 4018:4019 4020:4051 4052:4083 4084:4147 4148:4155 4156:4159 4160:4169 4170:4173 4174:4211 4212:4227 4.11 Power Down When inactive, the Transceiver/Framer Power Down mode ...
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SK70740/44 — HDSL2 Modem Chip Set 4.13 Microprocessor Interface The microprocessor interface provides access to internal control and status registers. The interface may be configured for either Motorola 68000 series or Intel 80C51 series microprocessors. The configuration of the interface ...
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Register Definitions The SK70740/44 registers are accessed by the system processor through the microprocessor interface. Upon reset, the registers are set to the default values shown in each register description table. Note that none of the registers, except PLL_CTL ...
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SK70740/44 — HDSL2 Modem Chip Set Table 8. AFE Control Register 1, AR1, R/W, Address = 00h, Default = 00h (Continued) Bit Name Transmit Buffer Load is high impedance. Default mode (TBLDHIMP = 0) assumes transmit buffer has to drive ...
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Transceiver/Framer Registers Table 10 shows the functional mapping of the Transceiver/Framer registers. summary of the Transceiver/Framer registers. descriptions of each register. Table 10. Transceiver/Framer Register Categories Address Range (hex ...
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SK70740/44 — HDSL2 Modem Chip Set Table 11. Transceiver/Framer Register Summary (Continued) Addr Register Label (hex) 30 PLL_CTL HTMCR 34- 86-92 93 84-9F A0 PLRATE HTFTCR A5 HTFBSR ...
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Table 11. Transceiver/Framer Register Summary (Continued) Addr Register Label (hex) C3 HRFFDR C4 C5 HRFTTCR C6 HRFNCR1 C7 HRFNCR2 C8 C9 HRFCRC CA HRFPAJ CB HRFPAC CC-D1 D2 HRFHOH1 D3 HRFHOH2 D4 HRFHOH3 D5 HRFHOH4 HRFFSW1 ...
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SK70740/44 — HDSL2 Modem Chip Set Table 13. Main Control Register 1, MAIN1, R/W Address = 01h, Default = 20h Bit Name <7:6> FEC_CTL 5 SYM_MAP <1:0> SLI Table 14. Activation Mode Control Register, ...
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Table 17. Interrupt Mask Register, INT_MSK Bit Name VAL FAIL logic 1 represents a masked condition. A logic zero is unmasked. Setting the mask ...
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SK70740/44 — HDSL2 Modem Chip Set 5.3.2 Registers 0Fh through 17h are Reserved Table 20. Rate Select 0 Register, RATE_SEL0, R/W, Address = 18h, Default = AAh Bit Name <7:0> D<7:0> Table 21. Rate Select 1 Register, RATE_SEL1, R/W, Address ...
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Registers 26h through 2Ch are Reserved Table 25. AFE Status Register, AFE_STAT, R/W, Address = 2Dh, Default = 00h Bit Name <7:0> D<7:0> 1. See “AFE Registers” on page 47 Table 26. Soft Decision (LSB) Register, SFT0, R, Address ...
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SK70740/44 — HDSL2 Modem Chip Set Table 30. Miscellaneous Control Register 1, MISC1, R/W, Address = 32h, Default = 00h Bit <7:6> 5 <4:3> <2:0> Table 31. Wander Reduction Control Register, HTMCR, R/W, Address = 33h, Default = 00h Bit ...
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Table 33. Code Generator 1, CG1, R/W, Address = 81h, Default = DAh Bit Name <7:4> rs Reserved. Must be’0’ when written. Code generator bits: When cgsel = 00, program decoder: <3:0> cg When cgsel = 10, program encoder: When ...
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SK70740/44 — HDSL2 Modem Chip Set complement of the FECNS register to determine the average noise power. The average FECNS value is then compared to the average signal power to determine the system SNR. For a PAM 16 constellation, the ...
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Table 40. Reference Transmit Water Level, HTFWL, R/W, Address = A1h, Default = 2Eh Bit Name <7:0> htfwl Table 41. Actual Transmit Water Level, TFWL, R, Address = A2h Bit Name <7:0> htfwl Actual water level for transmit FIFO. Granularity ...
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SK70740/44 — HDSL2 Modem Chip Set Table 43. Transmit Test Control Register, HTFTCR, R/W, Address = A4h, Default = 00h Bit Name 1 = disable writes to the transmit FIFO. The FIFO contents will be retransmitted every 80 bits. 2 ...
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Table 47. Transmit Frame Control Register, HTFTMR, R/W, Address = A8h, Default = 00h Bit Name 4 scram_nt 3 scram_en 2 frame_inh 1 send_state 0 send_nml Table 48. All 1’s / 0’s Control send_nml frame-inh 0 don’t care 1 1 ...
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SK70740/44 — HDSL2 Modem Chip Set 5.5.1 Registers ABh through B0h are Reserved Table 51. HDSL2 Transmit Overhead Register 1, HTFHOH1, R/W, Address = B1h, Default = 00h Bit Name 7 eoc10 6 eoc8 5 eoc7 4 eoc6 3 eoc5 ...
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Table 54. HDSL2 Transmit Overhead Register 4, HTFHOH4, R/W, Address = B4h, Default = 00h Bit Name 7 eoc17 6 segd 5 eoc9 4 sega 3 sb1 2 sb2 1 sb3 0 sb4 5.6 Framer Receive Registers Table 55. Receive ...
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SK70740/44 — HDSL2 Modem Chip Set Table 56. Receive Test Control Register, HRFTCR, R/W, Address = C1h, Default = 00h Bit Name <7:3> dis_cnt 1 diswr_m 0 rs 5.6.1 Receive FIFO Water Level The receive FIFO water level ...
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Table 59. Receive Status Register, HRFSR Register, R, Address = C4h Bit Name detflg crcerr 3 fcsync 2 fsdet 1 fsevent 0 dlempty Table 60. Receive Timing & Loopback Register, HRFTTCR, R/W, Address = ...
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SK70740/44 — HDSL2 Modem Chip Set adjustment variable and is set in the associated HRFPAJ (CAh) register. “ ” is the NCO clock division ratio variable and is set in the HRFPAC (CBh) register bit control ...
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Table 65. CRC Counter Register, HRFCRC, R, Address = C9h Bit Name <7:0> hrfcrc CRC error counter. The counter saturates at FFh and is reset with ercnt_rst in HRFCR. 5.6.3 Registers CCh through D1h are Reserved Table 66. HDSL2 Receive ...
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SK70740/44 — HDSL2 Modem Chip Set Table 68. HDSL2 Receive Overhead Register 3, HRFHOH3, R, Address = D4h Bit Name 2 eoc22 1 eoc21 0 eoc20 Table 69. HDSL2 Receive Overhead Register 4, HRFHOH4, R, Address = D5h Bit Name ...
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Analog Front End Test Specifications Note: Table 72 through Table 77 specifications of the SK70740 AFE and are guaranteed by test except, where noted, by design. The minimum and maximum values listed in recommended operating conditions specified in Table ...
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SK70740/44 — HDSL2 Modem Chip Set Table 74. DC Electrical Characteristics (Continued) Parameter Digital input Low voltage Digital input High voltage Digital output Low voltage Digital output High voltage Transmitter bias voltage (TTIP/TRING) Receive bias voltage (RTIP/RRING) 1. Typical values ...
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Table 77. AFE Interface Timing Specifications (see Figure 23) Parameter DAC<3:0>, RSDO and ACE setup time DAC<3:0>, RSDO and ACE hold time REFCLK to ADC<5:0> valid data REFCLK to RSDI valid data 1. Typical values are at 25° C and ...
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SK70740/44 — HDSL2 Modem Chip Set 7.0 Transceiver/Framer Test Specifications Note: Table 78 through Table 84 specifications of the SK70744 Transceiver/Framer and are guaranteed by test except, where noted, by design. The minimum and maximum values listed in over the ...
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Table 80. DC Electrical Characteristics (Continued) Parameter Input High voltage Output Low voltage Output High voltage 2, 4 Input leakage current Tristate leakage current Input capacitance (individual pins) Load capacitance DAC<3:0> 1. Typical values are at 25° C and are ...
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SK70740/44 — HDSL2 Modem Chip Set Table 82. AFE Control Interface Timing Specifications (see Figure 5 and Figure 25) Parameter RSDI setup time to REFCLK rising edge REFCLK rising edge to RSDI hold time RSDO delay from REFCLK rising edge ...
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Figure 26. TDM Interface Timing - T1 Transport Mode TCLK TFSYNC T DS TSER RSER RCLK RFSYNC Table 84. Transceiver/Framer Reset Timing Specification Parameter RST Low pulse width Table 85. Intel Bus Parallel I/O Timing Characteristics (see Figure 27) Parameter ...
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SK70740/44 — HDSL2 Modem Chip Set Table 86. Motorola Bus Parallel I/O Timing Characteristics (see Figure 27) DS Low pulse width Read data valid time after DS rising edge DS rising edge to write data hold time Valid address to ...
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Figure 27. Parallel Microprocessor Bus Interface Timing ALE RD AD<7:0> CS ALE WR AD<7:0> CS A<7:0> AD<7:0> A<7:0> AD<7:0> Datasheet HDSL2 Modem Chip Set — SK70740/44 T ALE T RW ...
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SK70740/44 — HDSL2 Modem Chip Set 8.0 Mechanical Specifications Figure 28. 64 Pin QFP Package 64-Pin Quad Flat Pack • Part Number SK70740HE • Extended Temperature Range (-40 ° ° PIN DETAIL 78 ...
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... Figure 29. 100 Pin QFP Package 100 -Pin Quad Flat Pack • Part Number SK70744HE • Extended Temperature Range (-40 ° ° PIN DETAIL Datasheet HDSL2 Modem Chip Set — SK70740/ e/2 B Millimeters Dim Min Max A – ...
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