AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 107

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

16.1
3714A–MICRO–7/11
Software Reset
The program sequence to feed or enable the watchdog timer is as follows:
Table 16-1.
The WDT time-out period is dependent on the system clock frequency.
A Software Reset of the AT89LP51RD2/ED2/ID2 is accomplished by writing the software reset
sequence 5AH/A5H to the WDTRST SFR. The WDT does not need to be enabled to generate
the software reset. A normal software reset will set the SWRST flag in WDTCON. However, if at
any time an incorrect sequence is written to WDTRST (i.e. anything other than 1EH/E1H or
5AH/A5H), a software reset will immediately be generated and both the SWRST and WDTOVF
flags will be set. In this manner an intentional software reset may be distinguished from a soft-
ware error-generated reset. The program sequence to generate a software reset is as follows:
A software reset has the same duration as the normal watchdog reset and will also generate a
reset pulse on the RST pin unless DISRTO is set.
WTO2
0
0
0
0
1
1
1
1
MOV WDTRST, #01Eh
MOV WDTRST, #0E1h
MOV WDTRST, #05Ah
MOV WDTRST, #0A5h
Watchdog Timer Time-out Period Selection
WDT Prescaler Bits
WTO1
0
0
1
1
0
0
1
1
AT89LP51RD2/ED2/ID2 Preliminary
WTO0
0
1
0
1
0
1
0
1
1024K x (TPS+1)
2048K x (TPS+1)
128K x (TPS+1)
256K x (TPS+1)
512K x (TPS+1)
(Clock Cycles)
16K x (TPS+1)
32K x (TPS+1)
64K x (TPS+1)
Period
()
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