AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 149

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

Table 19-6.
19.6.2
3714A–MICRO–7/11
30h
38h
Master Receiver Mode
Data byte has been
transmitted; NOT ACK has
been received
Arbitration lost in SLA+W
or data bytes
Status Codes for Master Transmitter Mode
In the Master Receiver mode, a number of data bytes are received from a slave transmitter. In
order to enter a Master mode, a START condition must be transmitted. The format of the follow-
ing address packet determines whether Master Transmitter or Master Receiver mode is to be
entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is
entered.
SSIE must be written to one to enable the Two-wire Serial Interface, STA must be written to one
to transmit a START condition and SI must be cleared. The TWI will then test the Two-wire
Serial Bus and generate a START condition as soon as the bus becomes free. After a START
condition has been transmitted, the SI flag is set by hardware, and the status code in SSCS will
be 08h (see
by writing SLA+R to SSDAT. Thereafter the SI bit should be cleared to continue the transfer.
When SLA+R has been transmitted and an acknowledgment bit has been received, SI is set
again and a number of status codes in SSCS are possible. Possible status codes in Master
mode are 38h, 40h or 48h. The appropriate action to be taken for each of these status codes is
detailed in
set high by hardware. This scheme is repeated until the last byte has been received. After the
last byte has been received, the MR should inform the ST by sending a NACK after the last
received data byte. The transfer is ended by generating a STOP condition or a repeated START
condition.
Load data byte
No action
No action
No action
No action
No action
Table
Table
19-7. Received data can be read from the SSDAT Register when the SI flag is
19-7). In order to enter MR mode, SLA+R must be transmitted. This is done
0
1
0
1
0
1
AT89LP51RD2/ED2/ID2 Preliminary
0
0
1
1
0
0
1
1
1
1
1
1
X
X
X
X
X
X
Data byte will be transmitted and ACK or NOT
ACK will be received
Repeated START will be transmitted
STOP condition will be transmitted and STO
flag will be reset
STOP condition followed by a START condition
will be transmitted and STO flag will be reset
Two-wire Serial Bus will be released and not
addressed slave mode entered
A START condition will be transmitted when the
bus becomes free
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