AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 144

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

Table 19-3.
Table 19-4.
Table 19-5.
19.5
144
SSCS Address = ABH
Not Bit Addressable
Symbol
SC
SSADR Address = ACH
Not Bit Addressable
Symbol
SA
GC
SSDAT Address = ADH
Not Bit Addressable
Symbol
SD
Bit
Bit
Bit
7-0
6-0
7-0
Using the TWI
AT89LP51RD2/ED2/ID2 Preliminary
SC7
SA6
SD7
Function
Two-wire Interface Status
The current status code of the TWI logic and serial bus. See
status codes. Note that the three least significant bits always read as zero. The Status code is valid only while SI remains
set.
Function
Two-wire Interface Slave Address
The TWI will only respond to slave addresses that match this 7-bit address.
General Call Enable
Set to enable General Call address (00h) recognition. Clear to disable General Call address recognition.
Function
Two-wire Interface Serial Data
Writes to SSDAT queue the next address or data byte for transmission. Reads from SSDAT return the last address or
data byte present on the bus. Writes/reads to/from SSDAT must occur only while SI is set. Writes to SSDAT while SI = 0
are ignored. Reads from SSDAT while SI = 0 may return random data.
7
7
7
SSCS – Two-Wire Status Register
SSADR – Two-Wire Address Register
SSDAT – Two-Wire Data Register
SC6
SA5
SD6
The AT89LP TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events,
like reception of a byte or transmission of a START condition. Because the TWI is interrupt-
based, the application software is free to carry on other operations during a TWI byte transfer.
Note that the TWI Interrupt Enable (ETWI) bit in IE2 together with the Global Interrupt Enable bit
in EA allow the application to decide whether or not assertion of the SI flag should generate an
6
6
6
SC5
SA4
SD5
5
5
5
SC4
SA3
SD4
4
4
4
SC3
SA2
SD3
3
3
3
Table 19-6
through
SA1
SD2
0
2
2
2
Table 19-10
Reset Value = 1111 1000B
Reset Value = 1111 1110B
Reset Value = 1111 1111B
SA0
SD1
0
1
1
1
for a description of the
SD0
GC
0
0
0
0
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