AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 129

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

18.1.2
18.1.3
18.1.4
3714A–MICRO–7/11
Master Output / Slave Input (MOSI)
Master Input / Slave Output (MISO)
Slave Select (SS)
This 1-bit signal is directly connected between the master device and all slave devices. The
MOSI line is used to transfer data in series from the master to the slave. Therefore, it is an out-
put signal from the master, and an input signal to a slave. A byte (8-bit word) is normally
transmitted most significant bit (MSB) first, least significant bit (LSB) last. The DORD bit in
SPSTA can change the data ordering to LSB first and MSB last. All devices on the same bus
should share the same data order. If multiple masters are present in a system, only one should
drive the MOSI line at a time.
This 1-bit signal is directly connected between all slave devices and a master device. The MISO
line is used to transfer data in series from a slave to the master. Therefore, it is an output signal
from the slave, and an input signal to the master. A byte (8-bit word) is transmitted most signifi-
cant bit (MSB) first, least significant bit (LSB) last. The DORD bit in SPSTA can change the data
ordering to LSB first anf MSB last. All devices on the same bus should share the same data
order. When multiple slaves are present in a system, only the slave with its SS input low will
drive MISO.
Each slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any
message for a slave. It is obvious that only one master can drive the network at a time. The mas-
ter may select each slave device by software through port pins. To prevent bus conflicts on the
MISO line, only one slave should be selected at a time by the master for a transmission.
In a master configuration, the SS line can be used in conjunction with the MODF flag in the SPI
Status register (SPSTA) to prevent multiple masters from driving MOSI and SCK (see Error
conditions).
A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.
The SS pin can be used as a general-purpose I/O if the following conditions are met:
Note:
The In-System Programming (ISP) interface also uses the SPI pins. Although the ISP protocol is
SPI-based, the SS pin has special meaning and must be driven by the master as a frame delim-
iter. SS cannot be tied to ground for ISP to function correctly.
When the SPI is configured as a Master (MSTR in SPCON is set), the operation of the SS pin
depends on the setting of the Slave Select Disable bit, SSDIS. If SSDIS = 1, the SS pin is a gen-
eral purpose output pin which does not affect the SPI system. Typically, the pin will be driving
the SS pin of an SPI Slave. If SSDIS = 0, SS must be held high to ensure Master SPI operation.
• The device is configured as a Master and the SSDIS control bit in SPCON is set. This kind of
• The Device is configured as a Slave with CPHA and SSDIS control bits set
configuration can be found when only one Master is driving the network and there is no way
that the SS pin could be pulled low. Therefore, the MODF flag in the SPSTA will never be
set
configuration can happen when the system comprises one Master and one Slave only.
Therefore, the device should always be selected and there is no reason that the Master uses
the SS pin to select the communicating Slave device.
(1)
1. Clearing SSDIS control bit does not clear MODF.
2. Special care should be taken when setting SSDIS control bit when CPHA = ’0’ because in this
.
mode the SS is used to start the transmission on some devices. This requirement does not
apply to the AT89LP51RD2/ED2/ID2 itself.
AT89LP51RD2/ED2/ID2 Preliminary
(2)
. This kind of
129