AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 160

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

20.1
160
Analog Input Muxes
AT89LP51RD2/ED2/ID2 Preliminary
Each comparator may be configured to cause an interrupt under a variety of output value condi-
tions by setting the CMx
interrupt flags CFx in ACSRx are set whenever the comparator outputs match the conditions
specified by CMx
rupt and must be cleared by software. Both comparators share a common interrupt vector. If
both comparators are enabled, the user needs to read the flags after entering the interrupt ser-
vice routine to determine which comparator caused the interrupt.
The CCS
parator outputs. Normally the outputs are sampled every clock system; however, the outputs
may also be sampled whenever Timer 0, Timer 1 or Timer 2 overflows. These settings allow the
comparators to be sampled at a specific time or to reduce the number of comparator events
seen by the system when using level sensitive modes. The raw value of the comparator outputs
can always be read from the CMPA and CMPB bits in AREF.
The comparators will continue to function during Idle mode. If this is not the desired behavior,
the comparators should be disabled before entering Idle. The comparators are always disabled
during Power-down mode.
The positive input terminal of each comparator may be connected to any of the four analog input
pins by changing the CSA
input pins, the comparator must be disconnected from its inputs by clearing the CONA or CONB
bits. The connection is restored by setting the bits again after the muxes have been modified.
The corresponding comparator interrupt should not be enabled while the inputs are being
changed, and the comparator interrupt flag must be cleared before the interrupt is re-enabled in
order to prevent an unintentional interrupt request.
The equivalent model for the analog input circuitry is illustrated in
applied to AINn is subjected to the pin capacitance and input leakage of that pin, regardless of
whether that channel is selected as input to the comparator. When the channel is selected, the
source must drive the input capacitance of the comparator through the series resistance (com-
bined resistance in the input path).
Figure 20-2. Equivalent Analog Input Model
CLR
ANL
...
ORL
ANL
SETB
1-0
EC
ACSRA, #0DFh ; Clear CONA to disconnect COMP A
ACSRA, #020h ; Set CONA to connect COMP A
ACSRA, #0EFh ; Clear any spurious interrupt
bits in AREF
EC
AINn
2-0.
C
The flags may be polled by software or may be used to generate an inter-
10 pF
PIN
2-0
=
(Table
1-0
; Disable comparator interrupts
; Modify CSA or RFA bits
; Re-enable comparator interrupts
bits in ACSRx (See
or CSB
20-3) control when the comparator interrupts sample the com-
1-0
bits in ACSRA and ACSRB. When changing the analog
10 kΩ
R
IN
=
Table 20-1
R
10 kΩ
or
MUX
Table
Figure
=
20-2). The comparator
21-2. An analog source
C
0.3 pF
CMP
<
3714A–MICRO–7/11