AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 191

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

Table 24-5.
Notes:
24.3
3714A–MICRO–7/11
Address
08H
09H
0AH
0BH
0CH
0D – 0EH
0FH
10H
11 – 12h
1. The default state from the factory for all fuses is FFh, except for the Tristate Ports and Bootloader Jump Bit, which are 00H.
2. Changes to these fuses will only take effect after a device POR.
3. Changes to these fuses will only take effect after the ISP session terminates by bringing RST inactive.
Flash Hardware Security
Clock Source B – CSB[0:1]
Fuse Name
X1/X2 Mode
OCD Enable
User Signature Programming
Tristate Ports
EEPROM Erase
Low Power Mode – LPM[0:1]
R1 Enable
Oscillator Select
User Configuration Fuse Definitions
The AT89LP51RD2/ED2/ID2 provides three Hardware Security Bits (or Lock Bits) for Flash
Code Memory and Data EEPROM security. Security bits can be left unprogrammed (FFh) or
programmed (00h) to obtain the protection levels listed in
erased (set to FFh) by Chip Erase. Lock bit mode 2 disables programming of all memory
spaces, including the User Signature Array and User Configuration Fuses. User fuses must be
programmed before enabling Lock bit mode 2 or 3. Lock bit mode 3 implements mode 2 and
also blocks reads from the code and data memories; however, reads of the User Signature
Array, Atmel Signature Array, and User Configuration Fuses are still allowed.
The Hardware Security bits only restrict the access of the SPI-based ISP interface. The Hard-
ware Security Bits will not disable the Bootloader or any programming initiated by the application
software using IAP.
(2)
Description
FFh: X1 Mode (System clock is divided-by-two)
00h: X2 Mode (System clock is not divided-by-two)
FFh: On-Chip Debug is Disabled
00h: On-Chip Debug is Enabled
FFh: Programming of User Signature Disabled
00h: Programming of User Signature Enabled
FFh: I/O Ports start in input-only mode (tristated) after reset
00h: I/O Ports start in quasi-bidirectional mode after reset
FFh: EEPROM is erased during chiperase
00h: EEPROM is not erased during chiperase
Selects source for the system clock when using OSCA:
LPM1
FFh
FFh
00h
00h
FFh: 5 MΩ resistor on XTAL1A Disabled
00h: 5 MΩ resistor on XTAL1A Enabled
00h: Boot from Oscillator B (AT89LP51ID2 Only)
FFh: Boot from Oscillator A
Selects source for the system clock when using OSCB (AT89LP51ID2 Only):
CSB1
FFh
FFh
00h
00h
AT89LP51RD2/ED2/ID2 Preliminary
LPM0
FFh
00h
FFh
00h
CSB0
FFh
00h
FFh
00h
Power Mode
Low Power Mode
Normal Mode
Extra Low Power Mode (F
Normal Mode
Selected Source
Low Frequency Crystal Oscillator on XTAL1B/XTAL2B (XTAL)
Low Frequency Crystal Oscillator on XTAL1B/XTAL2B (XTAL)
External Clock on XTAL1B (XCLK)
Internal 8 MHz RC Oscillator (IRC)
Table
OSC
24-6. Security bits can only be
≤ 1 MHz)
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