AT89S4051 Atmel Corporation, AT89S4051 Datasheet
AT89S4051
Specifications of AT89S4051
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AT89S4051 Summary of contents
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... Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the disabling all other chip functions until the next external interrupt or hardware reset. 8-bit Microcontroller with 2K/4K Bytes Flash AT89S2051 AT89S4051 3390E–MICRO–6/08 ...
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The on-board Flash program memory is accessible through the ISP serial interface. Holding RST active forces the device into a serial programming interface and allows the program mem- ory to be written to or read from, unless one or more ...
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Pin Description 4.1 VCC Supply voltage. 4.2 GND Ground. 4.3 Port 1 Port 8-bit bi-directional I/O port. Port pins P1.2 to P1.7 provide internal pull-ups. P1.0 and P1.1 require external pull-ups. P1.0 and P1.1 also serve ...
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RST Reset input. Holding the RST pin high for two machine cycles while the is running resets the device. Each machine cycle takes 6 or clock cycles. 4.6 XTAL1 Input to the inverting amplifier and input to the internal ...
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X2 Mode Description The clock for the entire circuit and peripherals is normally divided by 2 before being used by the CPU core and peripherals. This allows any cyclic ratio (duty cycle accepted on XTAL1 input. In ...
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Table 7-1. AT89S2051/S4051 SFR Map and Reset Values 0F8H B 0F0H 00000000 0E8H ACC 0E0H 00000000 0D8H PSW 0D0H 00000000 0C8H 0C0H IP SADEN 0B8H X0X00000 00000000 P3 0B0H 11111111 IE SADDR 0A8H 00X00000 00000000 0A0H SCON SBUF 98H 00000000 ...
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Restrictions on Certain Instructions The AT89S2051/S4051 is an economical and cost-effective member of Atmel’s family of micro- controllers. It contains 2K/4K bytes of Flash program memory fully compatible with the MCS-51 architecture, and can be programmed using ...
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Reset During reset, all I/O Registers are set to their initial values, the port pins are weakly pulled and the program starts execution from the Reset Vector, 0000H. The AT89S2051/S4051 CC has three sources of reset: ...
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Brown-out Reset The AT89S2051/S4051 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD is nominally 2.0V. The purpose of the ...
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Power Saving Modes The AT89S2051/S4051 supports two power-reducing modes: Idle and Power-down. These modes are accessed through the PCON register. 12.1 Idle Mode Setting the IDL bit in PCON enters idle mode. Idle mode halts the internal CPU clock. ...
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Reset Recovery from Power-down Wakeup from Power-down through an external reset is similar to the interrupt with PWDEX = 0. At the rising edge of RST, Power-down is exited, the is restarted, and an internal timer begins counting. The ...
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Interrupts The AT89S2051/S4051 provides 6 interrupt sources: two external interrupts, two timer inter- rupts, a serial port interrupt, and an analog comparator interrupt. These interrupts and the system reset each have a separate program vector at the start of ...
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Interrupt Registers Table 14-1. – Interrupt Enable Register A8H Bit Addressable EA EC Bit 7 6 Symbol Function Global enable/disable. All interrupts are disabled when When each interrupt source is ...
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Timer/Counters The AT89S2051/S4051 have two 16-bit Timer/Counters: Timer 0 and Timer 1. The Timer/Coun- ters are identical to those in the AT89C2051/C4051. For more detailed information on the Timer/Counter operation, please click on the document link below: http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF 16. ...
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TL1 will always count from 00h to FFh. The output on the Timer 1 (T1) pin will be high from when TL1 equals 00h until TL1 equals TH1 (see TL1 on overflow. Instead, TH1 is used strictly as a compare ...
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ANDed with the SADDR to create the “Given” address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will ...
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Table 17-1. SCON – Serial Port Control Register SCON Address = 98H Bit Addressable SM0/FE SM1 Bit 7 6 (1) (SMOD = 0/1) Symbol Function Framing error bit. This bit is set by the receiver when an invalid stop bit ...
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Analog Comparator A single analog comparator is provided in the AT89S2051/S4051. The comparator operation is such that the output is a logical “1” when the positive input AIN0 (P1.0]) is greater than the neg- ative input AIN1 (P1.1). Otherwise ...
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Analog Comparator Register . Table 20-1. – Analog Comparator Control & Status Register ACSR ACSR = 97H Not Bit Addressable – – Bit 7 6 Symbol Function Comparator Interrupt Flag. Set when the comparator output meets the conditions specified ...
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... Parallel Programming Specification Atmel’s AT89S2051/S4051 offers 2K/4K bytes of In-System Programmable Flash code memory. In addition, the device contains a 32-byte User Signature Row and a 32-byte read-only Atmel Signature Row. Table 21-1. Device # AT89S2051 AT89S4051 Figure 21-1. Flash Parallel Programming Device Connections Note: AT89S2051/S4051 20 Memory Organization Page Size ...
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... Bit 7 XTAL Osc Bypass Bit 6 User Row Programming Bit 5 x2 Clock Bit 4 Serial Programming Bit 1 Lock Bit 2 Bit 0 Lock Bit 1 10. Atmel Signature Bytes: AT89S2051: Address AT89S4051: Address 3390E–MICRO–6/08 Test Control P3.2 INC (1) RST 1.0 µs 12V L H 12V 0.1 µs 1.0 µs 12V 0.1 µ ...
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Power-up Sequence Execute the following sequence to power-up the device before programming. 1. Apply power between VCC and GND pins. 2. After V 3. Wait 4 ms for the internal Power-on Reset to timeout. 4. Bring P3.2 to “H” ...
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Chip Erase Function: 1. FFH programmed to every address location. 2. FFH programmed to User Signature Row if User Row Fuse bit is enabled. 3. Lockbit1 and Lockbit2 programmed to “unlock” state. Usage: 1. Apply “0001” TestCode to P3.7, ...
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Page Write 4K Code Function: 1. Programs 1 page ( bytes) of data into the Code Memory array. 2. X-address (page) determined by previous Load-X command. 3. Y-address (offset) incremented by positive pulse on XTAL1 ...
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Read 4K Code Function: 1. Read 1 page ( bytes) of data from the Code Memory array. 2. X-address (page) determined by previous Load-X command. 3. Y-address (offset) incremented by positive pulse on XTAL1. Usage: 1. Execute ...
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Page Write User Signature Row Function: 1. Programs bytes of data into the User Signature Row. 2. X-address (page) should be 00H from a previous Load-X command. 3. Y-address (offset) incremented by positive pulse on XTAL1. ...
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Read User Signature Row Function: 1. Reads bytes of data from the User Signature Row. 2. X-address (page) should be 00H from a previous Load-X command. 3. Y-address (offset) incremented by positive pulse on XTAL1. Usage: ...
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Read Atmel Signature Row Function: 1. Reads bytes of data from the Atmel Signature Row. 2. X-address (page) should be 01H from a previous Load-X command. 3. Y-address (offset) incremented by positive pulse on XTAL1. Usage: ...
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Write Lock Bits/User Fuses Function: 1. Program Lock Bits 1 and 2. 2. Program user fuses. Usage: 1) Apply “1111” TestCode to P3.7, P3.5, P3.4, P3.3. 3. Drive Port P1 with fuse data, bits [7:4] for fuses and bits ...
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Figure 32-2. Flash Programming and Verification Waveforms in Parallel Mode AT89S2051/S4051 30 3390E–MICRO–6/08 ...
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Table 32-1. Symbol PWRUP t POR t PSTP t HSTL t MSTP t MHLD t XTW t ASTP t AHLD t PGW t DSTP t DHLD t XLP t PHX t BLT t PHBL t ...
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... In-System Programming (ISP) Specification Atmel’s AT89S2051/S4051 offers 2K/4K bytes of In-System Programmable Flash code memory. In addition, the device contains a 32-byte User Signature Row and a 32-byte read-only Atmel Signature Row. Table 33-1. Device # AT89S2051 AT89S4051 Figure 33-1. ISP Programming Device Connections Note: AT89S2051/S4051 32 Memory Organization Page Size ...
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... Lock Bit Definitions: Bit 0 Lock Bit 1 Bit 1 Lock Bit 2 5. Atmel Signature Bytes: AT89S2051: Address AT89S4051: Address 3390E–MICRO–6/08 Byte 1 Byte 2 1010 1100 0101 0011 1010 1100 100x xxxx ...
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Power-up Sequence Execute this sequence to power-up the device before programming. 1. Apply power between VCC and GND pins. 2. Keep SCK (P1.7) at GND. 3. Wait 10 µs and bring RST to “H” crystal is ...
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Power-down Sequence Execute this sequence to power-down the device after programming. 1. Set XTAL1 to “L” crystal is not used. 2. Bring RST to “L”. 3. Tri-state MOSI (P1.5). Figure 37-1. ISP Power-down Sequence 38. ISP Byte ...
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... CC (2) Power-down Mode Notes: 1. Under steady state (non-transient) conditions, I Maximum I per port pin Maximum total I for all output pins (15 mA for AT89S4051 exceeds the test condition than the listed test conditions. 2. Minimum V for Power-down is 2V P1.0 and P1.1 are comparator inputs and have no internal pullups. They should not be left floating. ...
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External Clock Drive Waveforms 43. External Clock Drive Symbol Parameter 1/t Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL 3390E–MICRO–6/08 AT89S2051/S4051 V = 2.7V to ...
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Serial Port Timing: Shift Register Mode Test Conditions The values in this table are valid for V Symbol Parameter t Serial Port Clock Cycle Time XLXL t Output Data Setup to Clock Rising Edge QVXH t Output Data Hold ...
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I Test Condition, Active Mode, All Other Pins are Disconnected CC 49. I Test Condition, Idle Mode, All Other Pins are Disconnected CC 50. Clock Signal Waveform for CLCH CHCL V - ...
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I (Active Mode) Measurements CC AT89S2051/S4051 40 I Active @ 25 CC 4.00 3.50 3.00 2.50 2.00 1. Frequency (MHz) I Active @ 90 CC 4.00 3.50 3.00 2.50 2.00 1. ...
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I (Idle Mode) Measurements CC 54. I (Power Down Mode) Measurements CC 3390E–MICRO–6/08 I Idle vs. Frequency 25°C 3 2.5 2 1 Frequency (MHz Power-down CC 2.5 ...
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Ordering Information 55.1 Green Package Option (Pb/Halide-free) Speed Power (MHz) Supply Ordering Code AT89S2051/S4051-24PU 24 2.7V to 5.5V AT89S2051/S4051-24SU 20P3 20-lead, 0.300” Wide, Plastic Dual In-line Package (PDIP) 20S2 20-lead, 0.300” Wide, Plastic Gull Wing Small Outline (SOIC) AT89S2051/S4051 ...
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Package Information 56.1 20P3 – PDIP A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion ...
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SOIC AT89S2051/S4051 44 3390E–MICRO–6/08 ...
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Revision History Revision No. Revision D – Feb. 2007 Revision E – June 2008 3390E–MICRO–6/08 AT89S2051/S4051 History • Removed Preliminary Status. • Added the qualifier “x1 and x2 Modes” to the Static Operation range. • Changed the value ranges ...
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