AT89S4051 Atmel Corporation, AT89S4051 Datasheet - Page 15

• Manufacturer Part Number: AT89S4051
• Manufacturer: Atmel Corporation

Specifications of AT89S4051

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 24 MHz
• Cpu: 8051-12C
• Max I/o Pins: 15
• Uart: 1
• Sram (kbytes): 0.25
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 2
• Isp: SPI

17. UART
17.1
17.2
3390E–MICRO–6/08
Enhanced UART
Automatic Address Recognition
TL1 will always count from 00h to FFh. The output on the Timer 1 (T1) pin will be high from when
TL1 equals 00h until TL1 equals TH1 (see
TL1 on overflow. Instead, TH1 is used strictly as a compare value (see
Figure 16-3. Example of a PWM Output
The UART in the AT89S2051/S4051 operates the same way as the UART in the
AT89C2051/C4051. For more detailed information on the UART operation, please click on the
document link below:
In addition to all of its usual modes, the UART can perform framing error detection by looking for
missing stop bits, and automatic address recognition. The UART also fully supports multiproces-
sor communication as does the standard 80C51 UART.
When used for framing error detect, the UART looks for missing stop bits in the communication.
A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0
and the function of SCON.7 is determined by PCON.6 (SMOD0). If SMOD0 is set then SCON.7
functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE,
SCON.7 can only be cleared by software.
Automatic Address Recognition is a feature which allows the UART to recognize certain
addresses in the serial bit stream by using hardware to make the comparisons. This feature
saves a great deal of software overhead by eliminating the need for the software to examine
every serial address which passes by the serial port. This feature is enabled by setting the SM2
bit in SCON. In the 9-bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will
be automatically set when the received byte contains either the “Given” address or the “Broad-
cast” address. The 9-bit mode requires that the 9th information bit is a 1 to indicate that the
received information is an address and not data.
The 8-bit mode is called mode 1. In this mode the RI flag will be set if SM2 is enabled and the
information received has a valid stop bit following the 8 address bits and the information is either
a Given or Broadcast address.
Mode 0 is the Shift Register mode and SM2 is ignored.
Using the Automatic Address Recognition feature allows a master to selectively communicate
with one or more slaves by invoking the given slave address or addresses. All of the slaves may
be contacted by using the Broadcast address. Two special Function Registers are used to
define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define
which bits in the SADDR are to be used and which bits are “don’t care”. The SADEN mask can
http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF
TL1 Count
T1
00
01
Figure
10 . . . TH1
16-3). TH1 does not act as the reload value for
. . . FF
AT89S2051/S4051
00
Figure
. . .
16-2).
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