AT89S4051 Atmel Corporation, AT89S4051 Datasheet - Page 21

• Manufacturer Part Number: AT89S4051
• Manufacturer: Atmel Corporation

Specifications of AT89S4051

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 24 MHz
• Cpu: 8051-12C
• Max I/o Pins: 15
• Uart: 1
• Sram (kbytes): 0.25
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 2
• Isp: SPI

Table 21-2.
Notes:
3390E–MICRO–6/08
Mode
Chip Erase
Load X-Address
Page Write
Page Read
Page Write
Page Read
Write Fuse/Lock Bit
Read Fuse/Lock Bit
1. The internal Y-address counter is reset to 00H on the rising/falling edge of RST.
2. A positive pulse on XTAL1 loads the address data on Port P1 into the X-address (page) register and resets the Y-address.
3. A positive pulse on XTAL1 advances the Y-address counter.
4. A low pulse on P3.2 loads data from Port P1 for the current address. If another P3.2 low pulse does not arrive within 150 µs,
5. Internally timed for 4 ms.
6. Internally timed for 2 ms.
7. 00H must be loaded into the X-address before executing this command.
8. Will read User Signature if X-address is 00H, will read Atmel Signature if X-address is 01H.
9.
10. Atmel Signature Bytes:
(5)
(3)(4)(6)
(3)(4)(6)(7)
programming starts.
Fuse/Lock Bit Definitions:
(3)
(3)(8)(10)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 1
Bit 0
AT89S2051:
AT89S4051:
Parallel Programming Mode Command Summary
(2)
(5)(9)
(9)
XTAL Osc Bypass
User Row Programming
x2 Clock
Serial Programming
Lock Bit 2
Lock Bit 1
Code Memory
Code Memory
Sig. Row
Sig. Row
Address
Address
00H = 1EH
01H = 23H
02H = FFH
00H = 1EH
01H = 43H
02H = FFH
Enable = 0/Disable = 1
Enable = 0/Disable = 1
Enable = 0/Disable = 1
Enable = 0/Disable = 1
Locked = 0/Unlocked = 1
Locked = 0/Unlocked = 1
1.0 µs
1.0 µs
1.0 µs
1.0 µs
P3.2
H
H
H
H
Test Control
RST
12V
12V
12V
12V
12V
12V
12V
12V
(1)
0.1 µs
0.1 µs
0.1 µs
0.1 µs
0.1 µs
INC
L
L
L
P3.3
H
H
H
H
L
L
L
L
P3.4
Test Selects
H
H
H
L
L
L
L
L
AT89S2051/S4051
P3.5
H
H
H
H
L
L
L
L
P3.7
H
H
H
H
H
L
L
L
Data I/O
P1.7-0
D
D
D
D
D
D
D
XX
OUT
OUT
OUT
IN
IN
IN
IN
21