AT89S4051 Atmel Corporation, AT89S4051 Datasheet - Page 9

• Manufacturer Part Number: AT89S4051
• Manufacturer: Atmel Corporation

Specifications of AT89S4051

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 24 MHz
• Cpu: 8051-12C
• Max I/o Pins: 15
• Uart: 1
• Sram (kbytes): 0.25
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 2
• Isp: SPI

10.2
10.3
11. Clock Register
Table 11-1.
3390E–MICRO–6/08
Symbol
PWDEX
X2
CLKREG = 8FH
Not Bit Addressable
Bit
Brown-out Reset
External Reset
Function
Power-down Exit Mode. When PWDEX = 1, wake up from Power-down is externally controlled. When PWDEX = 0, wake
up from Power-down is internally timed.
When X2 = 0, the frequency (at XTAL1 pin) is internally divided by 2 before it is used as the device system frequency.
When X2 = 1, the divide by 2 is no longer used and the XTAL1 frequency becomes the device system frequency. This
enables the user to use a 6 MHz crystal instead of a 12 MHz crystal in order to reduce EMI. The X2 bit is initialized on
power-up with the value of the X2 user fuse and may be changed at runtime by software.
CLKREG
–
7
– Clock Register
The AT89S2051/S4051 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V
level during operation by comparing it to a fixed trigger level. The trigger level for the BOD is
nominally 2.0V. The purpose of the BOD is to ensure that if V
speed, the system will gracefully enter reset without the possibility of errors induced by incorrect
execution. When V
diately activated. When V
microcontroller after the timeout period has expired in approximately 2 ms.
The RST pin functions as an active-high reset input. The pin must be held high for at least two
machine cycles to trigger the internal reset. RST also serves as the In-System Programming
(ISP) enable input. ISP mode is enabled when the external reset pin is held high and the ISP
Enable fuse is set.
.
–
6
–
5
CC
decreases to a value below the trigger level, the Brown-out Reset is imme-
CC
increases above the trigger level, the BOD delay counter starts the
–
4
–
3
–
2
AT89S2051/S4051
CC
Reset Value = XXXX XX0XB
fails or dips while executing at
PWDEX
1
X2
0
CC
9