ATmega640 Atmel Corporation, ATmega640 Datasheet
ATmega640
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ATmega640 Summary of contents
Page 1
... Six/Twelve PWM Channels with Programmable Resolution from Bits (ATmega1281/2561, ATmega640/1280/2560) – Output Compare Modulator – 8/16-channel, 10-bit ADC (ATmega1281/2561, ATmega640/1280/2560) – Two/Four Programmable Serial USART (ATmega1281/2561, ATmega640/1280/2560) – Master/Slave SPI Serial Interface – Byte Oriented 2-wire Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – ...
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... Pin Configurations Figure 1-1. TQFP-pinout ATmega640/1280/2560 100 (OC0B) PG5 1 (RXD0/PCINT8) PE0 2 (TXD0) PE1 3 (XCK0/AIN0) PE2 4 (OC3A/AIN1) PE3 5 (OC3B/INT4) PE4 6 (OC3C/INT5) PE5 7 (T3/INT6) PE6 8 (CLKO/ICP3/INT7) PE7 9 VCC 10 GND 11 (RXD2) PH0 12 (TXD2) PH1 ...
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... Figure 1-2. CBGA-pinout ATmega640/1280/2560 Top view Table 1- Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 CBGA-pinout ATmega640/1280/2560 GND AREF PF0 PF2 AVCC PG5 PF1 PF3 PE2 PE0 PE1 ...
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... PB6 Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 INDEX CORNER The large center pad underneath the QFN/MLF package is made of metal and internally con- nected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board. ...
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... Overview The ATmega640/1280/1281/2560/2561 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega640/1280/1281/2560/2561 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...
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... The ATmega640/1280/1281/2560/2561 AVR is supported with a full suite of program and sys debugger/simulators, in-circuit emulators, and evaluation kits. 2549N– ...
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... Comparison Between ATmega1281/2561 and ATmega640/1280/2560 Each device in the ATmega640/1280/1281/2560/2561 family differs only in memory size and number of pins. Table 2-1. Configuration Summary Device Flash EEPROM ATmega640 64KB ATmega1280 128KB ATmega1281 128KB ATmega2560 256KB ATmega2561 256KB 2.3 Pin Descriptions 2.3.1 VCC Digital supply voltage. 2.3.2 GND Ground. ...
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... The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega640/1280/1281/2560/2561 as listed on 2.3.6 Port D (PD7..PD0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability ...
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... As inputs, Port L pins that are externally pulled low will source current if the pull-up resistors are activated. The Port L pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port L also serves the functions of various special features of the ATmega640/1280/2560 as listed on 2.3.14 RESET Reset input ...
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... AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con- nected to V through a low-pass filter. 2.3.18 AREF This is the analog reference pin for the A/D Converter. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 , even if the ADC is not used. If the ADC is used, it should be connected ...
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... The QTouch Library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library User Guide 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 ® ® QTouch Library provides a simple to use solution to realize touch sensitive inter- ® ...
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... While one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Block Diagram of the AVR Architecture Program Flash ...
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... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega640/1280/1281/2560/2561 has Extended I/O space from 0x60 - 0x1FF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...
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... The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Summary” on page 416 • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Summary” on page 416 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 “Instruction Set Summary” on page ...
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... The three indirect address registers X, Y, and Z are defined as described in 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 for detailed information. for detailed information. shows the structure of the 32 general purpose working registers in the CPU. ...
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... The initial value of the stack pointer is the last address of the internal SRAM. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two for ATmega640/1280/1281 and three for ATmega2560/2561 when the return address is pushed onto the Stack with subroutine call or interrupt ...
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... Harvard architecture and the fast-access Register File concept. This is the basic pipelin- ing concept to obtain MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 ...
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... The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 The Parallel Instruction Fetches and Instruction Executions T1 clk ...
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... SREG = cSREG; /* restore SREG value (I-bit) */ When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ...
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... A return from an interrupt handling routine takes five clock cycles. During these five clock cycles, the Program Counter (three bytes) is popped back from the Stack, the Stack Pointer is incre- mented by three, and the I-bit in SREG is set. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 ; set Global Interrupt Enable 20 ...
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... SRAM Data Memory Figure 8-2 on page 23 organized. The ATmega640/1280/1281/2560/2561 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instruc- tions. For the Extended I/O space from $060 - $1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used ...
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... An optional external data SRAM can be used with the ATmega640/1280/1281/2560/2561. This SRAM will occupy an area in the remaining address locations in the 64K address space. This area starts at the address following the internal SRAM. The Register file, I/O, Extended I/O and Internal SRAM occupies the lowest 4,608/8,704 bytes, so when using 64Kbytes (65,536 bytes) of External Memory, 60,478/56,832 Bytes of External Memory are available. See Memory Interface” ...
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... Figure 8-3. 8.3 EEPROM Data Memory The ATmega640/1280/1281/2560/2561 contains 4Kbytes of data EEPROM memory orga- nized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
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... Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 is likely to rise or fall slowly on power-up/down. This causes the device for some CC 35 ...
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... Assembly Code Example EEPROM_write: C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 (1) ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ...
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... BOD does not match the needed detection level, an external low V be used reset occurs while a write operation is in progress, the write operation will be com- pleted provided that the power supply voltage is sufficient. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 (1) ; Wait for completion of previous write sbic EECR,EEPE rjcmp EEPROM_read ...
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... I/O Memory The I/O space definition of the ATmega640/1280/1281/2560/2561 is shown in mary” on page All ATmega640/1280/1281/2560/2561 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
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... Overview When the eXternal MEMory (XMEM) is enabled, address space outside the internal SRAM becomes available using the dedicated External Memory pins (see 13-3 on page tion is shown in Figure 9-1. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 78, Table 13-9 on page 82, and Table 13-21 on page Figure 9-1. External Memory with Sector Select ...
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... The data setup time before G low (t wiring delay (dependent on the capacitive load). 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 • A15:8: High-order address bus (configurable number of bits) (this figure shows the wave forms without wait-states). When ALE goes from Figure 9-2 on page 30 ...
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... The skew between the internal and external clock (XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Conse- quently, the XMEM interface is not suited for synchronous operation. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 External SRAM Connected to the AVR AVR AD7:0 ...
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... Figure 9-3. System Clock (CLK Note: Figure 9-4. System Clock (CLK Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 External Data Memory Cycles without Wait-state (SRWn1=0 and SRWn0= CPU ALE A15:8 Prev. addr. DA7:0 Prev. data WR DA7:0 (XMBK = 0) Prev. data DA7:0 (XMBK = 1) Prev. data RD 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector) ...
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... Addressing above address 0xA1FF is not recommended, since this will address an external memory location that is already accessed by another (lower) address. To 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 External Data Memory Cycles with SRWn1 = 1 and SRWn0 = ...
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... Port Pin operation, the Memory Interface will address 0x0000 - 0x2FFF. See the following code examples. Care must be exercised using this option as most of the memory is masked away. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Address Map with 32Kbytes External Memory AVR Memory Map 0x0000 ...
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... Assembly Code Example C Code Example #define OFFSET 0x4000 void XRAM_example(void Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 (1) ; OFFSET is defined to 0x4000 to ensure ; external memory access ; Configure Port C (address high byte output 0x00 when the pins are released ; for normal Port Pin operation ldi r16, 0xFF ...
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... Erase and Write operations in two different operations. The Programming times for the different modes are shown in While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 – ...
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... When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft- ware can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 EEPROM Mode Bits Programming EEPM0 ...
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... It is possible to configure different wait-states for different External Memory addresses. The external memory address space can be divided in two sectors that have separate wait-state bits. The SRL2, SRL1, and SRL0 bits select the split of the sectors, see 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 ...
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... Note: 9.4.2 XMCRB – External Memory Control Register B Bit (0x75) Read/Write Initial Value 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 28. By default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire Sector limits with different settings of SRL2:0 SRL1 SRL0 ...
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... External Memory. Table 9-4. XMM2 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Port C Pins Released as Normal Port Pins when the External Memory is Enabled XMM1 XMM0 # Bits for External Memory Address (Full 56Kbytes space ...
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... Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 presents the principal clock systems in the AVR and their distribution. All of the 52. The clock systems are detailed below. ...
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... The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 10-1. Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 is halted, TWI address recognition in all sleep modes. I/O ASY Device Clocking Options Select Device Clocking Option ...
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... It gives the lowest power consumption, but is not capable of driving other clock inputs, and may be more susceptible to noise in noisy environments. In these cases, refer to the Crystal Oscillator” on page 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 to start oscillating and a minimum number of oscillating CC , the device issues an internal reset with a time-out delay (t ...
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... The CKSEL0 Fuse together with the SUT1:0 Fuses select the start-up times as shown in 10-4. Table 10-4. Oscillator Source / Power Conditions Ceramic resonator, fast Ceramic resonator, slowly Ceramic resonator, BOD 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Table 10-3. For ceramic resonators, the capacitor values given Low Power Crystal Oscillator Operating Modes (1) CKSEL3:1 (2) ...
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... The operating mode is selected by the fuses CKSEL3:1 as shown in Table 10-5. Frequency Range (MHz) Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Start-up Times for the Low Power Crystal Oscillator Clock Selection (Continued) Start-up Time from Power-down and Power-save 1K CK ...
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... Oscillator is selected, start-up times are determined by the SUT Fuses and CKSEL0 as shown in The Low-Frequency Crystal Oscillator provides an internal load capacitance, see each XTAL/TOSC pin. Table 10-7. Device ATmega640/1280/1281/2560/2561 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Start-up Times for the Full Swing Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save 258 CK rising power 258 CK ...
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... By default, the Internal RC Oscillator provides an approximate 8MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. See on page 371 with the CKDIV8 Fuse programmed. See 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Ce Table 10-7 on page Table 10-8. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection ...
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... This clock may be select as the system clock by programming the CKSEL Fuses to “11” as shown in Table 10-11. 128kHz Internal Oscillator Operating Modes Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 371. “Calibration Byte” on page Internal Calibrated RC Oscillator Operating Modes Frequency Range (MHz) 7 ...
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... MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is required, ensure that the MCU is kept in Reset during the changes. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Start-up Time from Power- down and Power-save BOD enabled ...
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... See on selecting external clock as input instead of a 32kHz crystal. 10.12 System Clock Prescaler The ATmega640/1280/1281/2560/2561 has a system clock prescaler, and the system clock can be divided by setting the used to decrease the system clock frequency and the power consumption when the requirement for processing power is low ...
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... The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor start up. This feature should be used if the selected clock 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 ...
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... Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 10-15. Clock Prescaler Select CLKPS3 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 CLKPS2 CLKPS1 ...
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... The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s requirements. 11.1 Sleep Modes ATmega640/1280/1281/2560/2561, and their distribution. The figure is helpful in selecting an appropriate sleep mode. sources. Table 11-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes. ...
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... SREG is set. If Timer/Counter2 is not running, Power-down mode is recommended instead of Power-save mode. The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save mode. If the Timer/Counter2 is not using the asynchronous clock, the Timer/Counter Oscillator is 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 “External Interrupts” on page 112 “Clock Sources” on page 41. 53 ...
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... ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 “Power-down Supply Current” on page 392 for details on ADC operation. “PRR0 – Power Reduction Register 0” on page 56 57, provides a method for stopping the clock for examples ...
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... In the deeper sleep modes, this will contribute significantly to the total current consumption. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 “AC – Analog Comparator” on page 271 for details on the start-up time. “Interrupts” on page 105 for details on how to configure the Watchdog Timer ...
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... Initial Value • Bit 7 - PRTWI: Power Reduction TWI Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up the TWI again, the TWI should be re initialized to ensure proper operation. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 – ...
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... Bit 3 - PRTIM3: Power Reduction Timer/Counter3 Writing a logic one to this bit shuts down the Timer/Counter3 module. When the Timer/Counter3 is enabled, operation will continue like before the shutdown. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 – ...
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... When waking up the USART2 again, the USART2 should be re initialized to ensure proper operation. • Bit 0 - PRUSART1: Power Reduction USART1 Writing a logic one to this bit shuts down the USART1 by stopping the clock to the module. When waking up the USART1 again, the USART1 should be re initialized to ensure proper operation. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 58 ...
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... SUT and CKSEL Fuses. The dif- ferent selections for the delay period are presented in 12.2 Reset Sources The ATmega640/1280/1281/2560/2561 has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • ...
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... A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V when V Figure 12-2. MCU Start-up, RESET Tied to V TIME-OUT INTERNAL 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Power-on Reset Circuit Brown-out Reset Circuit Pull-up Resistor SPIKE FILTER ...
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... Figure 12-4. External Reset During Operation 12.2.3 Brown-out Detection ATmega640/1280/1281/2560/2561 has an On-chip Brown-out Detection (BOD) circuit for moni- toring the V the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as ...
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... Time-out period t “Watchdog Timer” on page 55. Figure 12-6. Watchdog Reset During Operation 12.3 Internal Voltage Reference ATmega640/1280/1281/2560/2561 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 12.3.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used ...
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... Figure 12-7. Watchdog Timer 12.4.2 Overview ATmega640/1280/1281/2560/2561 has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode required that the system uses the WDR - Watchdog Timer Reset - instruction to restart the coun- ter before the time-out value is reached ...
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... The following code example shows one assembly and one C function for turning off the Watch- dog Timer. The example assumes that interrupts are controlled (for example by disabling interrupts globally) so that no interrupts will occur during the execution of these functions. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 64 ...
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... C Code Example void WDT_off(void Note: The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 (1) ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Clear WDRF in MCUSR in r16, MCUSR andi r16, (0xff & ...
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... Assembly Code Example WDT_Prescaler_Change: C Code Example void WDT_Prescaler_Change(void Notes: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 (1) ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence in r16, WDTCSR ori r16, (1<<WDCE) | (1<<WDE) out WDTCSR, r16 ; -- Got four cycles to set the new values from here - ...
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... This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config- ured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 – ...
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... Bit 5, 2:0 - WDP3:0: Watchdog Timer Prescaler and 0 The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run- ning. The different prescaling values and their corresponding time-out periods are shown in Table 12-2 on page 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Watchdog Timer Configuration (1) WDE WDIE ...
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... Table 12-2. WDP3 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 (2048) cycles (4096) cycles (8192) cycles 16K (16384) cycles ...
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... Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in Functions” on page nate functions. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 and Ground as indicated in CC for a complete list of parameters. Pxn ...
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... To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 (1) Pxn SLEEP ...
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... This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. page 73 value. The maximum and minimum propagation delays are denoted t respectively. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 summarizes the control signals for the pin value. Port Pin Configurations I/O Pull-up 0 ...
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... When reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in the clock. In this case, the delay tpd through the synchronizer is one system clock period. Figure 13-4. Synchronization when Reading a Software Assigned Pin Value INSTRUCTIONS 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 SYSTEM CLK XXX SYNC LATCH PINxn r17 Figure 13-4. The out instruction sets the “ ...
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... If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 (1) ... ; Define pull-ups and set outputs high ...
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... AVR microcon- troller family. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 or GND is not recommended, since this may cause excessive currents if the pin is CC shows how the port pin control signals from the simplified ...
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... Figure 13-5. Alternate Port Functions Pxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: PTOExn: Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 (1) PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 0 PVOExn PVOVxn 1 0 DIEOExn DIEOVxn ...
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... Refer to the alternate function description for further details. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 summarizes the function of the overriding signals. The pin and port indexes from are not shown in the succeeding tables. The overriding signals are Generic Description of Overriding Signals for Alternate Functions ...
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... DIEOV DI AIO Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Port A Pins Alternate Functions AD7 (External memory interface address and data bit 7) AD6 (External memory interface address and data bit 6) AD5 (External memory interface address and data bit 5) AD4 (External memory interface address and data bit 4) ...
Page 79
... Timer/Counter1 Output Compare C. The pin has to be configured as an output (DDB7 set (one)) to serve this function. The OC1C pin is also the output pin for the PWM mode timer function. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Overriding Signals for Alternate Functions in PA3:PA0 PA3/AD3 PA2/AD2 ...
Page 80
... DDB0 slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB0. When the pin is forced input, the pull-up can still be controlled by the PORTB0 bit. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 80 ...
Page 81
... DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 and Table 13-8 relate the alternate functions of Port B to the overriding signals Figure 13-5 on page 76. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the Overriding Signals for Alternate Functions in PB7:PB4 PB7/OC0A/OC1C PB6/OC1B ...
Page 82
... PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Port C Pins Alternate Functions Port Pin PC7 A15 (External Memory interface address bit 15) PC6 A14 (External Memory interface address bit 14) PC5 A13 (External Memory interface address bit 13) PC4 A12 (External Memory interface address bit 12) ...
Page 83
... The XCK1 pin is active only when the USART1 operates in Synchronous mode. • ICP1 – Port D, Bit 4 ICP1 – Input Capture Pin 1: The PD4 pin can act as an input capture pin for Timer/Counter1. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 PC3/A11 PC2/A10 SRE • (XMM<5) SRE • (XMM<6) ...
Page 84
... Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. Table 13-13 on page 85 the overriding signals shown in 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 and Table 13-14 on page 85 relates the alternate functions of Port D to Figure 13-5 on page 76. ...
Page 85
... DDOV PVOE PVOV DIEOE DIEOV Table 13-14. Overriding Signals for Alternate Functions in PD3:PD0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV AIO Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 PD7/T0 PD6/ INPUT T1 INPUT AIO – PD3/INT3/TXD1 PD2/INT2/RXD1 ...
Page 86
... Comparator Negative Input or Output Compare and PWM Output A for (Analog Comparator Positive Input or USART0 external clock input/output) (Programming Data Output or USART0 Transmit Pin) (Programming Data Input, USART0 Receive Pin or Pin Change Interrupt 8) 1. Only for ATmega1281/2561. For ATmega640/1280/2560 these functions are placed on MISO/MOSI pins. Table 13-15. ...
Page 87
... Synchronous mode. • PDO/TXD0 – Port E, Bit 1 PDO, SPI Serial Programming Data Output. During Serial Program Downloading, this pin is used as data output line for the ATmega1281/2561. For ATmega640/1280/2560 this function is placed on MISO. TXD0, USART0 Transmit pin. • PDI/RXD0/PCINT8 – Port E, Bit 0 PDI, SPI Serial Programming Data Input ...
Page 88
... AIO Table 13-17. Overriding Signals for Alternate Functions in PE3:PE0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI PE0 AIO Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 PE7/INT7/ICP3 PE6/INT6/ INT7 ENABLE INT6 ENABLE 1 INT7 INPUT/ICP3 INT7 INPUT/T3 INPUT INPUT – ...
Page 89
... I/O pin. • ADC3 – ADC0 – Port F, Bit 3:0 Analog to Digital Converter, Channel 3:0. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Alternate Function ADC7/TDI (ADC input channel 7 or JTAG Test Data Input) ADC6/TDO (ADC input channel 6 or JTAG Test Data Output) ...
Page 90
... PVOV DIEOE DIEOV 13.3.7 Alternate Functions of Port G The Port G alternate pin configuration is as follows: Table 13-21. Port G Pins Alternate Functions Port Pin PG5 PG4 PG3 PG2 PG1 PG0 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 PF7/ADC7/TDI PF6/ADC6/TDO JTAGEN JTAGEN 1 JTAGEN JTAGEN SHIFT_IR + 0 SHIFT_DR 0 JTAGEN 0 TDO JTAGEN ...
Page 91
... Table 13-22. Overriding Signals for Alternate Functions in PG5:PG4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV AIO 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 and Table 13-23 on page 92 Figure 13-5 on page — – – – – – – – – – ...
Page 92
... OC4C, Output Compare Match C output: The PH5 pin can serve as an external output for the Timer/Counter4 Output Compare C. The pin has to be configured as an output (DDH5 set) to serve this function. The OC4C pin is also the output pin for the PWM mode timer function. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 PG3/TOSC2 AS2 • EXCLK 0 AS2 • ...
Page 93
... When the USART2 forces this pin input, a logical on in PORTH0 will turn on the internal pull-up. Table 13-25. Overriding Signals for Alternate Functions in PH7:PH4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV AIO 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 PH7/ OC2B ENABLE 0 – INPUT – ...
Page 94
... XCK2, USART 2 External Clock. The Data Direction Register (DDJ2) controls whether the clock is output (DDJ2 set) or input (DDJ2 cleared). The XCK2 pin is active only when the USART2 operates in synchronous mode. PCINT11, Pin Change Interrupt Source 11. The PJ2 pin can serve as External Interrupt Sources. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 PH3/OC4A 0 0 XCK2 OUTPUT 0 ...
Page 95
... When the USART3 forces this pin input, a logical one in PORTJ0 will turn on the inter- nal pull-up. PCINT9, Pin Change Interrupt Source 9. The PJ0 pin can serve as External Interrupt Sources. Table 13-28 on page 96 the overriding signals shown in 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 and Table 13-29 on page 96 relates the alternate functions of Port J to Figure 13-5 on page 76. ...
Page 96
... Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.3.10 Alternate Functions of Port K The Port K alternate pin configuration is as follows: Table 13-30. Port K Pins Alternate Functions Port Pin 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 PJ7 PJ6/ PCINT15 PCINT15· ...
Page 97
... DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 PK4 ADC12/PCINT20 (ADC Input Channel 12 or Pin Change Interrupt 20) PK3 ADC11/PCINT19 (ADC Input Channel 11 or Pin Change Interrupt 19) PK2 ADC10/PCINT18 (ADC Input Channel 10 or Pin Change Interrupt 18) PK1 ADC9/PCINT17 (ADC Input Channel 9 or Pin Change Interrupt 17) ...
Page 98
... OC5A, Output Compare Match A output: The PL3 pin can serve as an external output for the Timer/Counter 5 Output Compare A. The pin has to be configured as an output (DDL3 set) to serve this function. The OC5A pin is also the output pin for the PWM mode timer function. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 PK3/ADC11/ PCINT19 0 ...
Page 99
... Table 13-35. Overriding Signals for Alternate Functions in PL3:PL0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV AIO 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 and Table 13-35 relates the alternate functions of Port L to the overriding signals Figure 13-5 on page 76. PL7 0 0 – – – – ...
Page 100
... Read/Write Initial Value 13.4.6 DDRB – Port B Data Direction Register Bit 0x04 (0x24) Read/Write Initial Value 13.4.7 PINB – Port B Input Pins Address Bit 0x03 (0x23) Read/Write Initial Value 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 JTD – – PUD R R for more details about this feature ...
Page 101
... Bit 0x09 (0x29) Read/Write Initial Value 13.4.14 PORTE – Port E Data Register Bit 0x0E (0x2E) Read/Write Initial Value 13.4.15 DDRE – Port E Data Direction Register Bit 0x0D (0x2D) Read/Write Initial Value 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 PORTC7 PORTC6 PORTC5 PORTC4 R/W R/W R/W R ...
Page 102
... DDRG – Port G Data Direction Register Bit 0x13 (0x33) Read/Write Initial Value 13.4.22 PING – Port G Input Pins Address Bit 0x12 (0x32) Read/Write Initial Value 13.4.23 PORTH – Port H Data Register Bit (0x102) Read/Write Initial Value 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 PINE7 PINE6 PINE5 PINE4 R/W R/W R/W R/W N/A N/A N/A N/A 7 ...
Page 103
... PORTK – Port K Data Register Bit (0x108) Read/Write Initial Value 13.4.30 DDRK – Port K Data Direction Register Bit (0x107) Read/Write Initial Value 13.4.31 PINK – Port K Input Pins Address Bit (0x106) Read/Write Initial Value 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 DDH7 DDH6 DDH5 DDH4 R/W R/W R/W R ...
Page 104
... PORTL – Port L Data Register Bit (0x10B) Read/Write Initial Value 13.4.33 DDRL – Port L Data Direction Register Bit (0x10A) Read/Write Initial Value 13.4.34 PINL – Port L Input Pins Address Bit (0x109) Read/Write Initial Value 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 PORTL7 PORTL6 PORTL5 PORTL4 R/W R/W R/W R ...
Page 105
... ATmega640/1280/1281/2560/2561. For a general explanation of the AVR interrupt handling, refer to 14 ...
Page 106
... When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. ATmega640/1280/2560. 3. Only available in Interrupt Definition 335. ...
Page 107
... Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 14-2. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega640/1280/1281/2560/2561 is: Address 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E ...
Page 108
... Reset and Interrupt Vector Addresses is: Address Labels Code 0x00000 RESET: ldi 0x00001 0x00002 0x00003 0x00004 0x00005 ; .org 0x1F002 0x1F002 0x1F004 ... 0x1FO70 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 jmp TIM3_COMPA jmp TIM3_COMPB jmp TIM3_COMPC jmp TIM3_OVF jmp USART1_RXC jmp USART1_UDRE jmp USART1_TXC ...
Page 109
... Moving Interrupts Between Application and Boot Section The MCU Control Register controls the placement of the Interrupt Vector table, see Code Exam- ple below. For more details, see 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Comments jmp EXT_INT0 jmp EXT_INT1 ... ... ...
Page 110
... IVSEL bit (see tion” on page 1. Write the Interrupt Vector Change Enable (IVCE) bit to one. 2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 ; Get MCUCR in r16, MCUCR mov r17, r16 ...
Page 111
... IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section ...
Page 112
... The start-up time is defined by the SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 15.1 Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 40. Figure 15-1 on page “Overview” on 113. 112 ...
Page 113
... Therefore recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Regis- ter before the interrupt is re-enabled. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 pcint_in_(0) pin_lat D Q ...
Page 114
... Table 15-3. ISCn1 Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 (1) Interrupt Sense Control ISCn0 0 The low level of INTn generates an interrupt request 1 Any edge of INTn generates asynchronously an interrupt request 0 The falling edge of INTn generates asynchronously an interrupt request ...
Page 115
... When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT15:8 pin will cause an inter- rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT15:8 pins are enabled individually by the PCMSK1 Register. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 ...
Page 116
... If PCINT23:16 is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT23:16 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 15.2.8 PCMSK1 – Pin Change Mask Register 1 Bit (0x6C) Read/Write Initial Value 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 – – – – R ...
Page 117
... Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the cor- responding I/O pin. If PCINT7:0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 ...
Page 118
... The Timer/Counter can be clocked internally, via the prescaler external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 “TQFP-pinout ATmega640/1280/2560” on page “Register Description” on page Count Clear ...
Page 119
... The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 16-2 shows a block diagram of the counter and its surroundings. Figure 16-2. Counter Unit Block Diagram 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 See “Output Compare Unit” on page 120. Table 16-1 are also used extensively throughout the document. Definitions The counter reaches the BOTTOM when it becomes 0x00 ...
Page 120
... Waveform Generator for handling the special cases of the extreme values in some modes of operation Figure 16-3 on page 121 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Increment or decrement TCNT0 by 1. Select between increment and decrement. Clear TCNT0 (set all bits to zero). ...
Page 121
... TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 DATA BUS OCRnx = ...
Page 122
... The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC0x state before the out- put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation. See 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 COMnx1 Waveform COMnx0 D ...
Page 123
... The timing diagram for the CTC mode is shown in (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then coun- ter (TCNT0) is cleared. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Table 16-2 on page 129, and for phase correct PWM refer to See “Compare Match Output Unit” on page 147. ...
Page 124
... In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 ...
Page 125
... OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1). The waveform generated will have a maximum frequency of f feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out- put Compare unit is enabled in the fast PWM mode. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 ...
Page 126
... OC0B pin (see visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 16-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating 1 Table 16-4 on page ...
Page 127
... MAX value in all modes other than phase correct PWM mode. Figure 16-8. Timer/Counter Timing Diagram, no Prescaling clk clk (clk TCNTn TOVn Figure 16-9 on page 128 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 f OCnxPCPWM Figure 16-7 on page 126 Figure 16-8 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled ...
Page 128
... PWM mode where OCR0A is TOP. Figure 16-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- clk clk (clk TCNTn (CTC) OCRnx OCFnx 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 I/O Tn /8) I/O MAX - 1 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC I/O Tn /8) ...
Page 129
... Table 16-3 mode. Table 16-3. COM0A1 Note: Table 16-4 on page 130 to phase correct PWM mode. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 COM0A1 COM0A0 COM0B1 R/W R/W R Table 16-2 shows the COM0A1:0 bit functionality when the WGM02:0 bits Compare Output Mode, non-PWM Mode COM0A0 ...
Page 130
... Table 16-6. COM0B1 Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Compare Output Mode, Phase Correct PWM Mode COM0A0 0 WGM02 = 0: Normal Port Operation, OC0A Disconnected 1 WGM02 = 1: Toggle OC0A on Compare Match Clear OC0A on Compare Match when up-counting. Set OC0A on 0 Set OC0A on Compare Match when up-counting. Clear OC0A ...
Page 131
... Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase cor- Compare Output Mode, Phase Correct PWM Mode COM0B0 0 1 Clear OC0B on Compare Match when up-counting. Set OC0B on 0 Set OC0B on Compare Match when up-counting. Clear OC0B ...
Page 132
... These bits are reserved bits and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see 16-9 on page 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 FOC0A FOC0B – ...
Page 133
... Initial Value The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC0B pin. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Clock Select Bit Description CS01 CS00 0 ...
Page 134
... OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the cor- responding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 – ...
Page 135
... When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Generation Mode Bit Description” on page 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 131. Table 16-8, “Waveform ...
Page 136
... The Power Reduction Timer/Counter4 bit, PRTIM4, in page 57 The Power Reduction Timer/Counter5 bit, PRTIM5, in page 57 Timer/Counter4 and Timer/Counter5 only have full functionality in the ATmega640/1280/2560. Input capture and output compare are not available in the ATmega1281/2561. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 “TQFP-pinout ATmega640/1280/2560” on page 2 4 ...
Page 137
... The double buffered Output Compare Registers (OCRnA/B/C) are compared with the Timer/Counter value at all time. The result of the compare can be used by the Waveform Gener- ator to generate a PWM or variable frequency output on the Output Compare pin (OCnA/B/C). 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Count Clear Direction ...
Page 138
... The same principle can be used directly for accessing the OCRnA/B/C and ICRn Registers. Note that when using “C”, the compiler handles the 16-bit access. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 The compare match event will also set the Compare 271). The Input Capture unit includes a digital filtering unit Definitions The counter reaches the BOTTOM when it becomes 0x0000 ...
Page 139
... The following code examples show how atomic read of the TCNTn Register contents. Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 (1) ... ; Set TCNTn to 0x01FF ldi r17,0x01 ...
Page 140
... Assembly Code Example TIM16_ReadTCNTn: C Code Example unsigned int TIM16_ReadTCNTn( void ) { } Note: The assembly code example returns the TCNTn value in the r17:r16 register pair. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 (1) ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ...
Page 141
... The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CSn2:0) bits located in the Timer/Counter control Register B (TCCRnB). For details on clock sources and prescaler, see 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 (1) ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ...
Page 142
... The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 shows a block diagram of the counter and its surroundings. DATA BUS (8-bit) ...
Page 143
... When the low byte is read the high byte is copied into the high byte Temporary Register (TEMP). When the CPU reads the ICRnH I/O location it will access the TEMP Register. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ...
Page 144
... Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICRn 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 138. “Accessing 16-bit Registers” (Figure 18-1 on page 169) ...
Page 145
... Compare unit (A/B/C). The elements of the block diagram that are not directly a part of the Out- put Compare unit are gray shaded. Figure 17-4. Output Compare Unit, Block Diagram 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 See “Modes of Operation” on page 148. shows a block diagram of the Output Compare unit. The small “n” in the register and DATA BUS TEMP (8-bit) OCRnxH Buf ...
Page 146
... Normal mode. The OCnx Register keeps its value even when changing between Waveform Generation modes. Be aware that the COMnx1:0 bits are not double buffered together with the compare value. Changing the COMnx1:0 bits will take effect immediately. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 138. “Accessing 16-bit Registers” 146 ...
Page 147
... The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COMnx1 tells the Waveform Generator that no action on the OCnx Register performed on the next compare match. For compare output actions in the 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Waveform Generator I/O for details. See “ ...
Page 148
... Note: For detailed timing information refer to 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Table 17-3 on page See “Compare Match Output Unit” on page 147. (1) WGMn0 Timer/Counter (PWMn0) Mode of Operation 0 0 Normal 0 1 PWM, Phase Correct, 8-bit 1 0 PWM, Phase Correct, 9-bit ...
Page 149
... CTC mode does not have the double buff- ering feature. If the new value written to OCRnA or ICRn is lower than the current value of 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 th bit, except that it is only set, not cleared. However, combined with the timer overflow ...
Page 150
... The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a compare match occurs. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 = f /2 when OCRnA is set to zero (0x0000). The waveform frequency is OC ...
Page 151
... The PWM waveform is generated by setting (or clearing) the OCnx Register at the compare match between OCRnx and TCNTn, and clearing (or setting) the OCnx Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 ...
Page 152
... The TCNTn value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a compare match occurs. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 f clk_I ---------------------------------- - ⋅ ...
Page 153
... The PWM waveform is generated by setting (or clearing) the OCnx Register at the compare match between OCRnx and TCNTn when the counter increments, and clearing (or setting) the OCnx Register at compare match between OCRnx and TCNTn when 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 ...
Page 154
... The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a compare match occurs. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 f OCnxPCPWM and Figure 17-9 on page 155 ...
Page 155
... TCNTn when the counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 shows the output generated is, in contrast to the phase correct mode, symmetri- ...
Page 156
... Flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for modes utilizing double buffering). Figure 17-10. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling Figure 17-11 Figure 17-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Figure 17-10 clk I/O clk Tn ...
Page 157
... The same renaming applies for modes that set the TOVn Flag at BOTTOM. Figure 17-12. Timer/Counter Timing Diagram, no Prescaling (PC and PFC PWM) Figure 17-13 Figure 17-13. Timer/Counter Timing Diagram, with Prescaler (f and ICF n 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 shows the count sequence close to TOP in various modes. When using phase and clk I/O clk Tn (clk ...
Page 158
... OCnC pin must be set in order to enable the output driver. When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is dependent of the WGMn3:0 bits setting. tionality when the WGMn3:0 bits are set to a normal or a CTC mode (non-PWM). 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 ...
Page 159
... Table 17-4 PWM mode. Table 17-4. COMnA1 COMnB1 COMnC1 Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Table 17-2 on page “Modes of Operation” on page Compare Output Mode, non-PWM COMnA0 COMnB0 COMnC0 0 Normal port operation, OCnA/OCnB/OCnC disconnected 1 Toggle OCnA/OCnB/OCnC on compare match 0 Clear OCnA/OCnB/OCnC on compare match (set output to low level) ...
Page 160
... ICPn pin for changing its output. The input capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM ...
Page 161
... This feature allows software control of the counting. 17.11.9 TCCR1C – Timer/Counter 1 Control Register C Bit (0x82) Read/Write Initial Value 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 and Figure 17-11 on page Clock Select Bit Description CSn1 CSn0 clock source. (Timer/Counter stopped) ...
Page 162
... These bits are reserved for future use. For ensuring compatibility with future devices, these bits must be written to zero when TCCRnC is written. 17.11.13 TCNT1H and TCNT1L – Timer/Counter 1 Bit (0x85) (0x84) Read/Write Initial Value 17.11.14 TCNT3H and TCNT3L – Timer/Counter 3 Bit (0x95) (0x94) Read/Write Initial Value 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 FOC3A FOC3B FOC3C – ...
Page 163
... Read/Write Initial Value 17.11.18 OCR1BH and OCR1BL – Output Compare Register 1 B Bit (0x8B) (0x8A) Read/Write Initial Value 17.11.19 OCR1CH and OCR1CL – Output Compare Register 1 C Bit (0x8D) (0x8C) Read/Write Initial Value 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 TCNT4[15:8] TCNT4[7:0] R/W R/W R/W R ...
Page 164
... Read/Write Initial Value 17.11.25 OCR4CH and OCR4CL –Output Compare Register 4 C Bit (0xAD) (0xAC) Read/Write Initial Value 17.11.26 OCR5AH and OCR5AL – Output Compare Register 5 A Bit (0x129) (0x128) Read/Write Initial Value 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 OCR3A[15:8] OCR3A[7:0] R/W R/W R/W R ...
Page 165
... Read/Write Initial Value 17.11.31 ICR4H and ICR4L – Input Capture Register 4 Bit (0xA7) (0xA6) Read/Write Initial Value 17.11.32 ICR5H and ICR5L – Input Capture Register 5 Bit (0x127) (0x126) Read/Write Initial Value 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 OCR5B[15:8] OCR5B[7:0] R/W R/W R/W R ...
Page 166
... When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (see TIFRn, is set. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 See “Accessing 16-bit Registers” on page 138 – ...
Page 167
... OCFnC is automatically cleared when the Output Compare Match C Interrupt Vector is exe- cuted. Alternatively, OCFnC can be cleared by writing a logic one to its bit location. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 “Interrupts” on page 105) is executed when the OCFnA Flag, located in 105) is executed when the TOVn Flag, located in TIFRn, is set. ...
Page 168
... TOVn Flag is set when the timer overflows. Refer to Flag behavior when using another WGMn3:0 bit setting. TOVn is automatically cleared when the Timer/Countern Overflow Interrupt Vector is executed. Alternatively, TOVn can be cleared by writing a logic one to its bit location. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Table 17-2 on page 148 for the TOVn 168 ...
Page 169
... The edge detector generates one clk = 6) edge it detects. Figure 18-1. Tn/T0 Pin Sampling Tn clk I/O 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 ). Alternatively, one of four taps from the prescaler can be used as a CLK_I/O pulse for each positive (CSn2 negative (CSn2 ...
Page 170
... When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared by hardware, and the Timer/Counters start counting simultaneously. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 < f /2) given a 50/50% duty cycle. Since the edge detector uses ExtClk ...
Page 171
... When this bit is one, Timer/Counter0, Timer/Counter1, Timer/Counter3, Timer/Counter4 and Timer/Counter5 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter0, Timer/Counter1, Timer/Counter3, Timer/Counter4 and Timer/Counter5 share the same prescaler and a reset of this prescaler will affect all timers. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 171 ...
Page 172
... Timer/Counter units and the port B pin 7 output driver circuit. Figure 19-2. Output Compare Modulator, Schematic COMA01 COMA00 COM1C1 COM1C0 ( From Waveform Generator ) ( From Waveform Generator ) 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 “Timer/Counter and 5 Prescaler” on page 169 OC1C Timer/Counter 1 OC0A Timer/Counter 0 Figure 19-1). D ...
Page 173
... PB7 output when PORTB7 equals zero. The period 2 high time is one cycle longer than the period 3 high time, but the result on the PB7 output is equal in both periods. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 illustrates the modulator in action. In this example the Timer/Counter1 is set to oper- clk I/O ...
Page 174
... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the The Power Reduction Timer/Counter2 bit, PRTIM2, in page 56 Figure 20-1. 8-bit Timer/Counter Block Diagram 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 “Pin Configurations” on page “Register Description” on page must be written to zero to enable Timer/Counter2 module. Count Clear ...
Page 175
... Operation of Timer/Counter2” on page prescaler, see 20.3 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 20-2 on page 176 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 ). T2 “Output Compare Unit” on page 180 Table 20-1 are also used extensively throughout the section. Definitions ...
Page 176
... PWM). For non-PWM modes the COM2x1:0 bits control whether the output should be set, cleared, or toggled at a compare match. For detailed timing information refer to 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 DATA BUS count clear TCNTn Control Logic ...
Page 177
... For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction for 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Figure 1 2 ...
Page 178
... The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 f clk_I/O = ...
Page 179
... TCNT2. Figure 20-5. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 20-5. The TCNT2 value is in the timing diagram shown as a histogram for illustrating when OCR2A is set to zero. This fea- oc2 clk_I/O OCnx Interrupt Flag Set ...
Page 180
... WGM22:0 bits and Compare Output mode (COM2x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (see 176). Figure 20-6 on page 181 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Table 20-4 on page f clk_I ----------------- - ⋅ ...
Page 181
... Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2x value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 DATA BUS OCRnx = (8-bit Comparator ) ...
Page 182
... The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC2x state before the out- put is enabled. Note that some COM2x1:0 bit settings are reserved for certain modes of operation. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Waveform Generator clk I/O See “ ...
Page 183
... Figure 20-9 Figure 20-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Table 20-5 on page contains timing data for basic Timer/Counter operation. The figure shows the I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. ...
Page 184
... Select clock source by setting AS2 as appropriate. 3. Write new values to TCNT2, OCR2x, and TCCR2x switch to asynchronous operation: Wait for TCN2UB, OCR2xUB, and TCR2xUB. 5. Clear the Timer/Counter2 Interrupt Flags. 6. Enable interrupts, if needed. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 shows the setting of OCF2A in all modes except CTC mode. clk I/O clk Tn ...
Page 185
... The recommended procedure for reading TCNT2 is thus as follows: 1. Write any value to either of the registers OCR2x or TCCR2x. 2. Wait for the corresponding Update Busy Flag to be cleared. 3. Read TCNT2. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 ) again becomes active, TCNT2 will read as the previous I/O 185 ...
Page 186
... Asynchronous Status Register” on page 192 For Timer/Counter2, the possible prescaled selections are: clk clk /128, clk T2S Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a predictable prescaler. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 clk clk I/O T2S Clear TOSC1 AS2 ...
Page 187
... Table 20-3 mode. Table 20-3. COM2A1 Note: Table 20-4 on page 188 to phase correct PWM mode. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 COM2A1 COM2A0 COM2B1 R/W R/W R Table 20-2 shows the COM2A1:0 bit functionality when the WGM22:0 bits Compare Output Mode, non-PWM Mode COM2A0 ...
Page 188
... Table 20-6. COM2B1 Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Compare Output Mode, Phase Correct PWM Mode COM2A0 0 WGM22 = 0: Normal Port Operation, OC2A Disconnected 1 WGM22 = 1: Toggle OC2A on Compare Match Clear OC2A on Compare Match when up-counting 0 Set OC2A on Compare Match when down-counting ...
Page 189
... Notes: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase cor- Compare Output Mode, Phase Correct PWM Mode COM2B0 0 1 Clear OC2B on Compare Match when up-counting 0 Set OC2B on Compare Match when down-counting ...
Page 190
... These bits are reserved bits and will always read as zero. • Bit 3 – WGM22: Waveform Generation Mode See the description in the • Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see 20-9 on page 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 FOC2A FOC2B – ...
Page 191
... Initial Value The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC2B pin. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Clock Select Bit Description CS21 CS20 0 ...
Page 192
... A logical zero in this bit indicates that TCCR2B is ready to be updated with a new value write is performed to any of the five Timer/Counter2 Registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 – ...
Page 193
... OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 – ...
Page 194
... If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the chronization Mode” on page 170 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 TSM – ...
Page 195
... SPI – Serial Peripheral Interface The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega640/1280/1281/2560/2561 and peripheral devices or between several AVR devices. The ATmega640/1280/1281/2560/2561 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • ...
Page 196
... In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high periods should be: Low period: longer than 2 CPU clock cycles. High period: longer than 2 CPU clock cycles. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 SHIFT ENABLE 196 ...
Page 197
... Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. For example, if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 Table 21-1. For more details on automatic port overrides, refer to 75. ...
Page 198
... SPI_MasterTransmit: Wait_Transmit: C Code Example void SPI_MasterInit(void void SPI_MasterTransmit(char cData Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 (1) ; Set MOSI and SCK output, all others input r17,(1<<DD_MOSI)|(1<<DD_SCK) ldi out DDR_SPI,r17 ; Enable SPI, Master, set clock rate fck/16 ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) out ...
Page 199
... Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 (1) ; Set MISO output, all others input ldi r17,(1<<DD_MISO) out DDR_SPI,r17 ; Enable SPI ldi r17,(1<<SPE) SPCR,r17 out ret ; Wait for reception complete ...
Page 200
... SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 21-2. CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 2549N–AVR–05/11 ATmega640/1280/1281/2560/2561 and Figure 21-4 on page 201. Data bits are shifted out and latched in on Table 21-3 on page 202 CPOL Functionality Leading Edge Sample (Rising) ...