ATmega640 Atmel Corporation, ATmega640 Datasheet - Page 38

• Manufacturer Part Number: ATmega640
• Manufacturer: Atmel Corporation

Specifications of ATmega640

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 86
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 1
• Uart: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 16
• Input Capture Channels: 4
• Pwm Channels: 15
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.4.2
2549N–AVR–05/11
XMCRB – External Memory Control Register B
Figure 9-1 on page
external memory address space is treated as one sector. When the entire SRAM address space
is configured as one sector, the wait-states are configured by the SRW11 and SRW10 bits.
Table 9-2.
• Bit 3:2 – SRW11, SRW10: Wait-state Select Bits for Upper Sector
The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the exter-
nal memory address space, see
• Bit 1:0 – SRW01, SRW00: Wait-state Select Bits for Lower Sector
The SRW01 and SRW00 bits control the number of wait-states for the lower sector of the exter-
nal memory address space, see
Table 9-3.
Note:
Bit
(0x75)
Read/Write
Initial Value
SRWn1
SRL2
0
0
1
1
0
0
0
1
1
1
1
1. n = 0 or 1 (lower/upper sector).
For further details of the timing and wait-states of the External Memory Interface, see
9-3
SRWn0
XMBK
Sector limits with different settings of SRL2:0
Wait States
through
R/W
0
1
0
1
7
0
SRL1
28. By default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire
0
1
1
0
0
1
1
Figures 9-6
Wait two cycles during read/write and wait one cycle before driving out new
R
6
–
0
(1)
SRL0
ATmega640/1280/1281/2560/2561
Table
Table
for how the setting of the SRW bits affects the timing.
x
0
1
0
1
0
1
R
5
–
0
9-3.
9-3.
Wait two cycles during read/write strobe
Wait one cycle during read/write strobe
R
4
–
0
No wait-states
R
3
–
0
Wait States
Upper sector = 0xA000 - 0xFFFF
Upper sector = 0xC000 - 0xFFFF
Upper sector = 0xE000 - 0xFFFF
Upper sector = 0x2200 - 0xFFFF
Upper sector = 0x4000 - 0xFFFF
Upper sector = 0x6000 - 0xFFFF
Upper sector = 0x8000 - 0xFFFF
Lower sector = 0x2200 - 0xBFFF
Lower sector = 0x2200 - 0xDFFF
Lower sector = 0x2200 - 0x3FFF
Lower sector = 0x2200 - 0x5FFF
Lower sector = 0x2200 - 0x7FFF
Lower sector = 0x2200 - 0x9FFF
address
Lower sector = N/A
XMM2
R/W
Sector Limits
2
0
XMM1
R/W
1
0
XMM0
R/W
0
0
XMCRB
Figures
38