ATmega644PR231 Atmel Corporation, ATmega644PR231 Datasheet - Page 139

• Manufacturer Part Number: ATmega644PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega644PR231

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

Figure 11-8. Packet Structure - High Data Rate Frame Buffer Read Access
11.3.4
11.3.5
8111C–MCU Wireless–09/09
MOSI
MISO
High Data Rate Energy Detection
High Data Rate Mode Options
0
byte 1 (command byte)
0
PHY_STATUS
1
reserved[5:0]
during Frame Buffer read access the last byte transferred after the PSDU data is the ED value
rather than the LQI value.
Figure 11-8 on page 139
access.
According to IEEE 802.15.4 the ED measurement duration is 8 symbol periods. For frames
operated at higher data rates the automated ED measurement duration is reduced to 32 µs to
take the reduced frame length into account, refer to
page
During Frame Buffer read access the ED value is appended to the PSDU data, refer to
11.3.3 “High Data Rate Frame Buffer Access” on page
Receiver Sensitivity Control
The different data rates between PPDU header (SHR and PHR) and PHY payload (PSDU)
cause a different sensitivity between header and payload. This can be adjusted by defining sen-
sitivity threshold levels of the receiver. With a sensitivity threshold level set (register bits
RX_PDT_LEVEL > 0), the receiver does not receive frames with an RSSI level below that
threshold. Under these operating conditions the receiver current consumption is reduced by
about 500 µA, refer to
ter 12.8.4.
Enabling receiver sensitivity control with at least RX_PDT_LEVEL = 1 is recommended for the 2
Mb/s rate with a PSDU sensitivity of -89 dBm. In the case of receiving with the default setting of
RX_PDT_LEVEL, a high data rate frame may be detected even if the PSDU sensitivity is above
the received signal strength. In this case the frame is rejected.
A description of the settings to control the sensitivity threshold with register 0x15 (RX_SYN) can
be found in
Reduced Acknowledgment Timing
On higher data rates the IEEE 802.15.4 compliant acknowledgment frame response time of
192 µs significantly reduces the effective data rate of the network. To minimize this influence in
Extended Operating Mode RX_AACK, refer to
Automatic ACK” on page
32 µs.
a frame with a data rate of 2000 kb/s and a PSDU length of 80 symbols. The PSDU length of the
acknowledgment frame is 5 octets according to IEEE 802.15.4.
91.
Figure 11-9 on page 140
Section 9.1.4 “Register Description” on page
byte 2 (data byte)
PHR[7:0]
XX
Section 12.8 “Current Consumption Specifications” on page 161
illustrates the packet structure of a High Data Rate Frame Buffer read
51, the acknowledgment frame response time can be reduced to
byte 3 (data byte)
PSDU[7:0]
illustrates an example for a reception and acknowledgement of
XX
Section 7.2.3 “RX_AACK_ON - Receive with
byte n-1 (data byte)
PSDU[7:0]
Section 8.4 “Energy Detection (ED)” on
138.
103.
XX
byte n (data byte)
ED[7:0]
AT86RF231
XX
parame-
Section
139