ATmega644PR231 Atmel Corporation, ATmega644PR231 Datasheet - Page 41
ATmega644PR231
Manufacturer Part Number
ATmega644PR231
Description
Manufacturer
Atmel Corporation
Specifications of ATmega644PR231
Flash (kbytes)
64 Kbytes
Max. Operating Frequency
20 MHz
Max I/o Pins
32
Spi
3
Twi (i2c)
1
Uart
2
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
AES
Sram (kbytes)
4
Eeprom (bytes)
2048
Operating Voltage (vcc)
1.8 to 3.6
Timers
3
Frequency Band
2.4 GHz
Max Data Rate (mb/s)
2
Antenna Diversity
Yes
External Pa Control
Yes
Power Output (dbm)
3
Receiver Sensitivity (dbm)
-101
Receive Current Consumption (ma)
13.2
Transmit Current Consumption (ma)
14.4
Link Budget (dbm)
104
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7.1.4.4
7.1.4.5
8111C–MCU Wireless–09/09
BUSY_TX and RX_ON States
Reset Procedure
The transition from PLL_ON to BUSY_TX state and subsequent to RX_ON state is shown in
Figure 7-6 on page
Figure 7-6.
Starting from PLL_ON state it is further assumed that the PLL is already locked. A transmission
is initiated either by a rising edge of pin 11 (SLP_TR) or by command TX_START. The PLL set-
tles to the transmit frequency and the PA is enabled.
t
the internally generated SHR is transmitted. After that the PSDU data are transmitted from the
Frame Buffer.
After completing the frame transmission, indicated by IRQ_3 (TRX_END), the PLL settles back
to the receive frequency within t
If during TX_BUSY the radio transmitter is programmed to change to a receive state it automati-
cally proceeds the state change to RX_ON state after finishing the transmission.
The radio transceiver reset procedure is shown in
Figure 7-7.
Note:
TR10
= 16 µs after initiating the transmission the AT86RF231 changes into BUSY_TX state and
Pin
State
Block
Command
Time
Event
State
Block
Pin /RST
Time
Timing figure t
Timing Characteristics” on page
PLL_ON to BUSY_TX to RX_ON Timing
Reset Procedure
various
XOSC, DVREG
PLL_ON
41.
TR13
0
PLL
or command TX_START
refers to
>t10
SLP_TR
TR11
Table 7-1 on page
0
x
= 32 µs in state PLL_ON.
t
157.
TR10
PA
x + 10
>t11
16
BUSY_TX
t
TR13
42, t
Figure 7-7 on page
FTN
PA, TX
10
, t
11
RX_ON
x + 40
refers to
XOSC, DVREG
[IRQ_4 (AWAKE_END)]
TRX_OFF
Section 12.4 “Digital Interface
x
RX_ON
41.
t
PLL
TR11
AT86RF231
x + 32
Time [µs]
RX
Time [µs]
41
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