ATtiny13 Atmel Corporation, ATtiny13 Datasheet - Page 21

• Manufacturer Part Number: ATtiny13
• Manufacturer: Atmel Corporation

Specifications of ATtiny13

• Flash (kbytes): 1 Kbytes
• Pin Count: 8
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 6
• Ext Interrupts: 6
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.06
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

5.5.3
2535J–AVR–08/10
EECR – EEPROM Control Register
• Bit 7 – Res: Reserved Bit
This bit is reserved for future use and will always read as 0 in ATtiny13. For compatibility with
future AVR devices, always write this bit to zero. After reading, mask out this bit.
• Bit 6 – Res: Reserved Bit
This bit is reserved in the ATtiny13 and will always read as zero.
• Bits 5:4 – EEPM[1:0]: EEPROM Programming Mode Bits
The EEPROM Programming mode bits setting defines which programming action that will be
triggered when writing EEPE. It is possible to program data in one atomic operation (erase the
old value and program the new value) or to split the Erase and Write operations in two different
operations. The Programming times for the different modes are shown in
While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be
reset to 0b00 unless the EEPROM is busy programming.
Table 5-1.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant inter-
rupt when Non-volatile memory is ready for programming.
• Bit 2 – EEMPE: EEPROM Master Program Enable
The EEMPE bit determines whether writing EEPE to one will have effect or not.
When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the
selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been
written to one by software, hardware clears the bit to zero after four clock cycles.
• Bit 1 – EEPE: EEPROM Program Enable
The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM.
When EEPE is written, the EEPROM will be programmed according to the EEPMn bits setting.
The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no
EEPROM write takes place. When the write access time has elapsed, the EEPE bit is cleared by
hardware. When EEPE has been set, the CPU is halted for two cycles before the next instruction
is executed.
Bit
Read/Write
Initial Value
EEPM1
0
0
1
1
EEPM0
EEPROM Mode Bits
0
1
0
1
R
7
–
0
Programming
R
6
–
0
3.4 ms
1.8 ms
1.8 ms
Time
–
EEPM1
R/W
X
5
Operation
Erase and Write in one operation (Atomic Operation)
Erase Only
Write Only
Reserved for future use
EEPM0
R/W
X
4
EERIE
R/W
3
0
EEMPE
R/W
2
0
EEPE
R/W
X
1
Table 5-1 on page
EERE
R/W
0
0
EECR
21.
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