ATtiny167 Automotive Atmel Corporation, ATtiny167 Automotive Datasheet
ATtiny167 Automotive
Specifications of ATtiny167 Automotive
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ATtiny167 Automotive Summary of contents
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Features • High Performance, Low Power Atmel AVR • Advanced RISC Architecture – 123 Powerful Instructions – Most Single Clock Cycle Execution – General Purpose Working Registers – Fully Static Operation • Non-volatile Program and Data Memories ...
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Description 1.1 Comparison Between ATtiny87 and ATtiny167 ATtiny87 and ATtiny167 are hardware and software compatible. They differ only in memory sizes as shown in Table 1-1. Device ATtiny167 ATtiny87 1.2 Part Description The ATtiny87/167 is a low-power CMOS 8-bit ...
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Automotive Quality Grade The ATtiny87/167 have been developed and manufactured according to the most stringent requirements of the international standard ISO-TS-16949. This data sheet contains limit val- ues extracted from the results of extensive characterization (temperature and voltage). The ...
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Block Diagram Figure 1-1. ATtiny87/ATtiny167 4 Block Diagram Watchdog Power Timer Supervision POR / BOD & Watchdog RESET Oscillator Oscillator Flash Circuits / Clock Generation EEPROM Timer/Counter-1 Timer/Counter-0 SPI & USI Analog Comp. PORT B (8) PORT A (8) ...
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Pin Configuration Figure 1-2. Pinout ATtiny87/167 - SOIC20 & TSSOP20 (RXLIN / RXD / ADC0 / PCINT0) PA0 (TXLIN / TXD / ADC1 / PCINT1) PA1 (MISO / DO / OC0A / ADC2 / PCINT2) PA2 (INT1 / ISRC ...
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Pin Description 1.7.1 Vcc Supply voltage. 1.7.2 GND Ground. 1.7.3 AVcc Analog supply voltage. 1.7.4 AGND Analog ground. 1.7.5 Port A (PA7..PA0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The ...
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AVR CPU Core 2.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access mem- ories, perform calculations, ...
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Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look ...
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SREG – AVR Status Register The AVR Status Register – SREG – is defined as: Bit Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to ...
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General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output ...
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Figure 2-3. X-register Y-register Z-register In the different addressing modes these address registers have functions as fixed displace- ment, automatic increment, and automatic decrement (see the instruction set reference for details). 2.5 Stack Pointer The Stack is mainly used for ...
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Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk the chip. No internal clock division is used. Figure 2-4 Harvard architecture and the fast ...
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Interrupt behavior When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt ...
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When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. Assembly Code Example C Code Example 2.7.2 Interrupt Response Time The interrupt execution response for ...
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AVR Memories This section describes the different memories in the ATtiny87/167. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny87/167 features an EEPROM Memory for data storage. All ...
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Timing diagrams for instruction fetch and execution are presented in Execution Timing” on page Figure 3-1. 3.2 SRAM Data Memory Figure 3-2 The ATtiny87/167 is a complex microcontroller with more peripheral units than can be sup- ported within the 64 ...
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Figure 3-2. 3.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk Figure 3-3. 3.3 EEPROM Data Memory The ATtiny87/167 contains EEPROM memory ...
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EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in ever, lets the user software detect when the next byte can be written. If the user ...
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The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator fre- quency is within the requirements described in page The following code examples show one assembly and one C function for erase, write, or atomic write ...
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The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execu- tion of these functions. Assembly Code Example C Code Example 3.3.6 Preventing ...
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Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an ...
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Bit 7:1 – Reserved Bits These bits are reserved for future use and will always read ATtiny87/167. • Bits 8:0 – EEAR8:0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL – specifies the high ...
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Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant interrupt ...
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System Clock and Clock Options The ATtiny87/167 provides a large number of clock sources. They can be divided into two cat- egories: internal and external. Some external clock sources can be shared with the asynchronous timer. After reset, the ...
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CPU Clock – clk CPU The CPU clock is routed to parts of the system concerned with the AVR core operation. Exam- ples of such modules are the General Purpose Register File, the Status Register and the Data memory ...
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The various choices for each clocking option are given in the following sections. When the CPU wakes up from Power-down or Power-save, or when a new clock source is enabled by the dynamic clock switch circuit, the selected clock source ...
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Table 4-3. Notes: When this Oscillator is selected, start-up times are determined by the SUT Fuses or by CSUT field as shown in Table 4-4. SUT1..0 CSUT1..0 Notes: 4.2.3 128 KHz Internal Oscillator The 128 KHz internal Oscillator is a ...
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Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in a ceramic resonator may be used. C1 and C2 should always be ...
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The CKSEL0 Fuse together with the SUT1..0 Fuses or CSEL0 together with CSUT1..0 field select the start-up times as shown in Table 4-7. CKSEL0 CSEL0 Notes: 4.2.5 Low-frequency Crystal Oscillator To use a 32.768 kHz watch crystal as the clock ...
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Figure 4-3. When this oscillator is selected, start-up times are determined by the SUT fuses or by CSUT field as shown in Table 4-8. SUT1..0 CSUT1..0 Notes: 4.2.6 External Clock To drive the device from this external clock source, CLKI ...
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Table 4-9. SUT1..0 CSUT1..0 Notes: Note that the System Clock Prescaler can be used to implement run-time changes of the inter- nal clock frequency while still ensuring stable operation. Refer to page 37 4.2.7 Clock Output Buffer If not using ...
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Command status return. The ‘Request Clock Availability ’ command returns status via the CLKRDY bit in the CLKCSR register. The ‘Recover System Clock Source ’ command returns a code of the current clock source in the CLKSELR register. This ...
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Clock Source’ command. This will indicate via the CLKRDY bit in the CLKCSR register that a valid clock source is available and operational. The ‘Disable Clock Source’ command disables the clock source indicated by the settings of CLKSELR register (only ...
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It is strongly recommended to run this sequence only once the interrupts have been disabled. The user (code) is responsible for the correct implementation of the clock switching sequence. Here is a “light” C-code that describes such a sequence of ...
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In the first domain, the user (code) can easily check the validity of the clock(s) Command” on page In the second domain, the lack of a clock results in the code not running. Thus, the presence of the system clock ...
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Here is a “light” C-code of a clock switching function using automatic clock monitoring. C Code Example ATtiny87/ATtiny167 36 void ClockSwiching (unsigned char clk _ #define CLOCK RECOVER 0x05 _ #define CLOCK ENABLE 0x02 _ #define CLOCK SWITCH 0x04 _ ...
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System Clock Prescaler 4.4.1 Features The ATtiny87/167 system clock can be divided by setting the Clock Prescaler Register – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can ...
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Incrementing CAL6.. will give a frequency increment of less than 2% in the frequency range 7.3 - 8.1 MHz. 4.5.2 CLKPR – Clock Prescaler Register Bit Read/Write Initial Value • Bit 7 – CLKPCE: Clock Prescaler ...
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Table 4-10. CLKPS3 4.5.3 CLKCSR – Clock Control & Status Register Bit Read/Write Initial Value • Bit 7 – CLKCCE: Clock Control Change Enable The CLKCCE bit must be written to logic one to enable change of the CLKCSR bits. ...
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The user’s code has to differentiate between ‘no_clock_signal’ and ‘clock_signal_not_yet_available’ condition. • Bits 3:0 – CLKC3:0: Clock Control Bits These bits define the command ...
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Bits 5:4 – CSUT1:0: Clock Start-up Time CSUT bits are initialized with the values of SUT Fuse bits. In case of ‘Enable/Disable Clock Source’ command, CSUT field provides the code of the clock start-up time. Refer to subdivisions of ...
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Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s ...
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BOD Disable When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, 226, the BOD is actively monitoring the power supply voltage during a sleep period. To save power possible to disable the BOD by software for ...
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Power-down Mode When the SM1..0 bits are written to 10, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the external Oscillator is stopped, while the external inter- rupts, the USI start condition, and the Watchdog ...
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Minimizing Power Consumption There are several possibilities to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected ...
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Watchdog Timer If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes and hence always consume power. In the ...
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Table 5-2. • Bit 0 – SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode ...
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Bit5 - PRLIN: Power Reduction LIN / UART controller Writing a logic one to this bit shuts down the LIN by stopping the clock to the module. When waking up the LIN again, the LIN should be re initialized ...
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System Control and Reset 6.1 Reset 6.1.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be ...
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Figure 6-1. BODLEVEL [2..0] 6.1.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in detection level. The POR circuit can be used to trigger the start-up Reset, as well ...
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Figure 6-3. TIME-OUT INTERNAL 6.1.4 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see not running. Shorter pulses are not guaranteed to generate a reset. ...
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Figure 6-5. 6.1.6 Watchdog System Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t Refer ...
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Bit 1 – EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • Bit 0 – PORF: Power-on ...
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Figure 6-7. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode required that the system uses the WDR - Watchdog Timer Reset - instruction to restart ...
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The following code example shows one assembly and one C function for turning off the Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling inter- rupts globally) so that no interrupts will occur during the execution of ...
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The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. Assembly Code Example C Code Example Notes: 6.3.2 Clock monitoring The Watchdog Timer can be used to detect a loss ...
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Watchdog Timer Control Register - WDTCR Bit Read/Write Initial Value • Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is con- figured for interrupt. ...
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Bit 3 - WDE: Watchdog System Reset Enable WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets ...
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Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny87/167. For a general explanation of the AVR interrupt handling, refer to dling” on page 7.1 Interrupt Vectors in ATtiny87/167 Table 7-1. Reset and Interrupt Vectors ...
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Program Setup in ATtiny87 The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATtiny87 is (2-byte step - using “rjmp” instruction): Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A ...
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Program Setup in ATtiny167 The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATtiny167 is (4-byte step - using “jmp” instruction): Address 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 ...
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External Interrupts 8.1 Overview The External Interrupts are triggered by the INT1..0 pins or any of the PCINT15..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT1..0 or PCINT15..0 pins are configured as outputs. This ...
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External Interrupts Register Description 8.3.1 External Interrupt Control Register A – EICRA The External Interrupt Control Register A contains control bits for interrupt sense control. Read/Write Initial Value • Bit 7..4 – Res: Reserved Bits These bits are unused ...
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Bit 1 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 ...
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Bit 1 - PCIE1: Pin Change Interrupt Enable 1 When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT15..8 ...
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Pin Change Mask Register 0 – PCMSK0 Read/Write Initial Value • Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0 Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set ...
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I/O-Ports 9.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...
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Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. tional description of one I/O-port pin, here generically called Pxn. Figure 9-2. Note: 9.2.1 Configuring the Pin Each port pin consists of three register ...
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Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI assembler instruction can be used to toggle one single bit in a port. 9.2.3 Break-Before-Make ...
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Table 9-1 Table 9-1. DDxn Note: 9.2.5 Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As shown in constitute ...
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Figure 9-5. The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and ...
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Digital Input Enable and Sleep Modes As shown in Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down or Power-save mode to avoid high power consumption if some input signals ...
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Figure 9-6. Pxn Note: 7728G–AVR–06/10 (1) Alternate Port Functions PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 0 PVOExn PVOVxn 1 0 DIEOExn DIEOVxn 1 SLEEP 0 PUOExn: Pxn PULL-UP OVERRIDE ENABLE PUOVxn: Pxn PULL-UP OVERRIDE VALUE DDOExn: Pxn DATA DIRECTION ...
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Table 9-2 Figure 9-6 nally in the modules having the alternate function. Table 9-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate ...
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MCU Control Register – MCUCR Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured ...
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Alternate Functions of Port A The Port A pins with alternate functions are shown in Table 9-3. ATtiny87/ATtiny167 76 Port A Pins Alternate Functions Port Pin Alternate Function PCINT7 (Pin Change Interrupt 7) ADC7 (ADC Input Channel 7) PA7 ...
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The alternate pin configuration is as follows: • PCINT7/ADC7/AIN1/XREF/AREF – Port A, Bit7 PCINT7: Pin Change Interrupt, source 7. ADC7: Analog to Digital Converter, channel 7. AIN1: Analog Comparator Positive Input. This pin is directly connected to the positive input ...
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PCINT3/ADC3/ISRC/INT1 – Port A, Bit 3 PCINT3: Pin Change Interrupt, source 3. ADC3: Analog to Digital Converter, channel 3. ISCR: Current Source Output pin. While current is sourced by the Current Source module, INT1: External Interrupt, source 1. The ...
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Table 9-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 7728G–AVR–06/10 Overriding Signals for Alternate Functions in PA7..PA4 PA7/PCINT7/ ADC7/AIN1 PA6/PCINT6/ /XREF/AREF ADC6/AIN0/SS 0 SPE & MSTR 0 PORTA6 & PUD 0 SPE & MSTR ...
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Table 9-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATtiny87/ATtiny167 80 Overriding Signals for Alternate Functions in PA3..PA0 PA3/PCINT3/ADC3/ PA2/PCINT2/ADC2/ ISRC/INT1 OC0A/DO/MISO 0 SPE & MSTR PORTA3 & PUD PORTA2 & PUD 0 SPE ...
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Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 9-6. Port Pin The alternate pin configuration is as follows: • PCINT15/ADC10/OC1BX/RESET/dW – Port B, Bit 7 PCINT15: Pin Change Interrupt, source 15. ...
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RESET: Reset input pin. When the RSTDISBL Fuse is programmed, this pin functions as a dW: When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unpro- • PCINT14/ADC9/OC1AX/INT0 – Port B, Bit 6 PCINT14: Pin Change Interrupt, ...
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PCINT10/OC1AV/USCK/SCL – Port B, Bit 2 PCINT10: Pin Change Interrupt, source 10. OC1AV: Output Compare and PWM Output A-V for Timer/Counter1. The PB2 pin has to be USCK: Three-wire Mode USI Clock Input. SCL: Two-wire Mode USI Clock Input. ...
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Table 9-7 in Figure 9-6 on page Table 9-7. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATtiny87/ATtiny167 84 and Table 9-8 relate the alternate functions of Port B to the overriding signals shown 73. ...
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Table 9-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 7728G–AVR–06/10 Overriding Signals for Alternate Functions in PB3..PB0 PB3/PCINT11/ PB2/PCINT10/ OC1BV OC1AV/USCK/SCL (USI_2_WIRE & 0 USIPOS) (USI_SCL_HOLD | 0 PORTB2) & ...
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Register Description for I/O Ports 9.4.1 Port A Data Register – PORTA Bit Read/Write Initial Value 9.4.2 Port A Data Direction Register – DDRA Bit Read/Write Initial Value 9.4.3 Port A Input Pins Register – PINA Bit Read/Write Initial ...
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Timer/Counter0 and Asynchronous Operation Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: 10.1 Features • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width ...
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Figure 10-1. 8-bit Timer/Counter0 Block Diagram The Timer/Counter (TCNT0) and Output Compare Register (OCR0A) are 8-bit registers. Inter- rupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with ...
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Definitions The following definitions are used extensively throughout the section: BOTTOM MAX TOP 10.3 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The clock source is selected by the ...
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Depending on the mode of operation used, the counter is cleared, incremented, or decre- mented at each timer clock (clk source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02 the timer is ...
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The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of ...
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Figure 10-4. Compare Match Output Logic 10.6.1 Compare Output Function The general I/O port function is overridden by the Output Compare (OC0A) from the Wave- form Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction ...
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For detailed timing information refer to 10.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply ...
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For generating a waveform output in CTC mode, the OC0A output can be set to toggle its log- ical level on each compare match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value ...
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The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of ...
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Figure 10-7. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The interrupt flag can be used to generate an interrupt each time the counter reaches ...
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Timer/Counter Timing Diagrams The following figures show the Timer/Counter in synchronous mode, and the timer clock (clk 0) is therefore shown as a clock enable signal. In asynchronous mode, clk T replaced by the Timer/Counter Oscillator clock. The figures ...
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Figure 10-11 Figure 10-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with clk clk (clk TCNTn (CTC) OCRnx OCFnx 10.9 Asynchronous Operation of Timer/Counter0 When Timer/Counter0 operates asynchronously, some considerations must be taken. • Warning: When switching between ...
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TOSC1 cycle to be reset. If the time between wake-up and re-entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the user is in doubt whether ...
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Timer/Counter0 Prescaler Figure 10-12. Prescaler for Timer/Counter0 XTAL2 XTAL1 The clock source for Timer/Counter0 is named clk main system I/O clock clk nously clocked from the XTAL oscillator or XTAL1 pin. This enables use of Timer/Counter0 as a Real ...
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When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM01:0 bit setting. bits are set to a normal or CTC mode (non-PWM). Table 10-1. COM0A1 Table 10-2 mode. Table 10-2. COM0A1 Note: Table ...
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Bit 6, 3 – WGM01:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used, see operation supported by the ...
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The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table Table 10-5. CS02 10.11.2 Timer/Counter0 Register – TCNT0 Bit Read/Write Initial Value The Timer/Counter Register gives direct access, both for read and write ...
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Bit 5 – AS0: Asynchronous Timer/Counter0 When AS0 is written to zero, Timer/Counter0 is clocked from the I/O clock, clkI/O and the Timer/Counter0 acts as a synchronous peripheral. When AS0 is written to one, Timer/Counter0 is clocked from the ...
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Timer/Counter0 Interrupt Mask Register – TIMSK0 Bit Read/Write Initial Value • Bit 7:2 – Res: Reserved Bits These bits are reserved in the ATtiny87/167 and will always read as zero. • Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match ...
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General Timer/Counter Control Register – GTCCR Bit Read/Write Initial Value • Bit 1 – PSR0: Prescaler Reset Timer/Counter0 When this bit is one, the Timer/Counter0 prescaler will be reset. This bit is normally cleared immediately by hardware. If the ...
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Timer/Counter1 Prescaler 11.1 Overview Most bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number. 11.1.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting ...
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The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1 pin to the counter is updated. Enabling and disabling of the clock input must be ...
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Timer/Counter1 Prescalers Register Description 11.2.1 General Timer/Counter Control Register – GTCCR Bit Read/Write Initial Value • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value ...
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Timer/Counter1 The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: 12.1 Features • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units ...
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Figure 12-1. 16-bit Timer/Counter1 Block Diagram Note: 12.2.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Reg- ister (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described ...
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The Timer/Counter can be clocked internally, via the prescaler external clock source on the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The ...
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Code Examples The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for access- ing the OCR1A/B and ICR1 Registers. Note that ...
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The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example C Code Example Note: The ...
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The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example C Code Example Note: The ...
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Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 12-2. Counter Unit Block Diagram Signal description (internal signals): The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High ...
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The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 12.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can ...
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Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O loca- tion before the low byte is written to ICR1L. For more information on how to access the 16-bit registers refer to ters” on ...
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Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1A/B). If TCNT equals OCR1A/B the comparator signals a match. A match will set the Output Compare Flag (OCF1A/B) at the next timer clock cycle. ...
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The OCR1A/B Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1A/B Buffer Register, and if double buff- ering is disabled the CPU will access the OCR1A/B ...
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Figure 12-6 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COM1A/B1:0 and OCnxi ...
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Figure 12-6. Compare Match Output Logic 12.8.1 Compare Output Function The general I/O port function is overridden by the Output Compare (OC1A/B) from the Wave- form Generator if either of the COM1A/B1:0 bits are set and if OCnxi respective bit ...
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COM1A/B1:0 bits as shown in For detailed timing information refer to 12.9.1 Normal Mode The simplest mode of operation is the Normal mode (WGM13:0 = 0). In ...
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An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt ...
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In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13 7), the value in ICR1 (WGM13:0 = 14), or the value in ...
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Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. How- ever, if the base PWM frequency is ...
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In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13 3), the value in ICR1 (WGM13:0 = 10), or the value ...
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It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no differences between the ...
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In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and ...
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In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1A/B pins. Setting the COM1A/B1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting ...
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Figure 12-12. Timer/Counter Timing Diagram, Setting of OCF1A/B, with Prescaler (f Figure 12-13 and frequency correct PWM mode the OCR1A/B Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 ...
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Figure 12-14. Timer/Counter Timing Diagram, with Prescaler (f 12.11 16-bit Timer/Counter Register Description 12.11.1 Timer/Counter1 Control Register A – TCCR1A Bit Read/Write Initial Value • Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A • Bit 5:4 – COM1B1:0: ...
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Table 12-2 PWM mode. Table 12-2. OC1Ai OC1Bi Note: Table 12-3 phase correct or the phase and frequency correct, PWM mode. Table 12-3. OC1Ai OC1Bi Note: • Bit 3:2 – ...
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Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the count- ing sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform ...
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Timer/Counter1 Control Register B – TCCR1B Bit Read/Write Initial Value • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from ...
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If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 12.11.3 Timer/Counter1 Control Register C ...
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Timer/Counter1 – TCNT1H and TCNT1L Bit Read/Write Initial Value The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both ...
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Input Capture Register – ICR1H and ICR1L Bit Read/Write Initial Value The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). ...
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Timer/Counter1 Interrupt Flag Register – TIFR1 Bit Read/Write Initial Value • Bit 7..6 – Reserved Bits These bits are reserved for future use. • Bit 5 – ICF1: Input Capture Flag This flag is set when a capture event ...
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SPI - Serial Peripheral Interface The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATtiny87/167 and peripheral devices or between several AVR devices. The ATtiny87/167 SPI includes the following features: 13.1 Features • Full-duplex, Three-wire Synchronous ...
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The interconnection between Master and Slave CPUs with SPI is shown in system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the ...
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When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overrid- den according to Port Functions” on page Table 13-1. MOSI MISO SCK Note: The following code examples show how to initialize the ...
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Assembly Code Example C Code Example Note: 7728G–AVR–06/10 (1) SPI_MasterInit: ; Set MOSI and SCK output, all others input r17,(1<<DD_MOSI)|(1<<DD_SCK) ldi out DDR_SPI,r17 ; Enable SPI, Master, set clock rate fck/16 r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) ldi SPCR,r17 out ret SPI_MasterTransmit: ; Start transmission ...
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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example C Code Example Note: ATtiny87/ATtiny167 144 (1) SPI_SlaveInit: ; Set MISO output, all others input r17,(1<<DD_MISO) ldi ...
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SS Pin Functionality 13.2.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so ...
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Bit 5 – DORD: Data Order When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted ...
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SPI Status Register – SPSR Bit Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set and ...
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Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in ure 13-3 SCK signal, ensuring sufficient ...
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USI – Universal Serial Interface 14.1 Features • Two-wire Synchronous Data Transfer (Master or Slave) • Three-wire Synchronous Data Transfer (Master or Slave) • Data Received Interrupt • Wakeup from Idle Mode • In Two-wire Mode: Wake-up from All ...
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A transparent latch is inserted between the USI Data Register Output and output pin, which delays the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data ...
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The clock is generated by the Master device software by toggling the USCK pin via the PORT Register or by writing a one to the USITC bit in USICR. Figure 14-3. Three-wire Mode, Timing Diagram CYCLE USCK USCK DO The ...
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The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO and USCK pins are enabled as output in the DDRA or DDRB Register. The value stored in register r16 prior to the ...
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SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ... SlaveSPITransfer: SlaveSPITransfer_loop: The code is size optimized using only eight instructions (+ ret). The code example assumes that the ...
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Figure 14-4. Two-wire Mode Operation, Simplified Diagram Figure 14-4 Slave only the physical layer that is shown since the system operation is highly depen- dent of the communication scheme used. The main differences between the Master and Slave ...
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Referring to the timing diagram 1. The a start condition is generated by the Master by forcing the SDA low line while the 2. In addition, the start detector will hold the SCL line low after the Master has forced ...
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Alternative USI Usage When the USI unit is not used for serial communication, it can be set alternative tasks due to its flexible design. 14.4.1 Half-duplex Asynchronous Data Transfer By utilizing the USI Data Register in ...
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Note that the corresponding Data Direction Register to the pin must be set to one for enabling data output from the USI Data Register. 14.5.2 USIBR – USI Buffer Register Bit Read/Write Initial Value • Bits 7:0 – USID7..0: USI ...
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Bits 3:0 – USICNT3..0: Counter Value These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or written by the CPU. The 4-bit counter increments by one for each clock generated either by ...
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Table 14-1. USIWM1 Note: • Bit 3:2 – USICS1:0: Clock Source Select These bits set the clock source for the USI Data Register and counter. The data output latch ensures that the output is changed at the opposite edge of ...
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Table 14-2. USICS1 • Bit 1 – USICLK: Clock Strobe Writing a one to this bit location strobes the USI Data Register to shift one step and the coun- ter to increment by ...
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USIPP – USI Pin Position Bit Read/Write Initial Value • Bits 7:1 – Res: Reserved Bits These bits are reserved bits in the ATtiny87/167 and always reads as zero. • Bit 0 – USIPOS: USI Pin Position Setting or ...
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LIN / UART - Local Interconnect Network Controller or UART The LIN (Local Interconnect Network serial communications protocol which efficiently supports the control of mechatronics nodes in distributed automotive applications. The main properties of the LIN bus ...
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LIN Protocol 15.3.1 Master and Slave A LIN cluster consists of one master task and several slave tasks. A master node contains the master task as well as a slave task. All other nodes contain a slave task only. ...
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Data Transport Two types of data may be transported in a frame; signals or diagnostic messages. • Signals Signals are scalar values or byte arrays that are packed into the data field of a frame. A signal is always ...
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LIN Overview The LIN/UART controller is designed to match as closely as possible to the LIN software appli- cation structure. The LIN software application is developed as independent tasks, several slave tasks and one master task (c.f. forms to ...
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LIN/UART Controller Structure Figure 15-4. LIN/UART Controller Block Diagram CLK IO RxD 15.4.4 LIN/UART Command Overview Figure 15-5. LIN/UART Command Dependencies ATtiny87/ATtiny167 166 Prescaler Sample /bit BAUD_RATE Get Byte Frame Time-out RX Synchronization Monitoring Data FIFO Tx Header IDOK ...
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Table 15-1. LENA 0 1 15.4.5 Enable / Disable Setting the LENA bit in LINCR register enables the LIN/UART controller. To disable the LIN/UART controller, LENA bit must be written wait states are implemented, so, the disable ...
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Tx Header Function In accordance with the LIN protocol, only the master task must enable this function. The header is sent in the appropriate timed slots at the programmed baud rate (c.f. LINBRR & LIN- BTR registers). The controller ...
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Handling Data of LIN response A FIFO data buffer is used for data of the LIN response. After setting all parameters in the LIN- SEL register, repeated accesses to the LINDAT register perform data read or data write (c.f. ...
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LIN / UART Description 15.5.1 Reset The AVR core reset logic signal also resets the LIN/UART controller. Another form of reset exists, a software reset controlled by LSWRES bit in LINCR register. This self-reset bit per- forms a partial ...
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Configuration Depending on the mode (LIN or UART), LCONF[1..0] bits of the LINCR register set the con- troller in the following configuration Table 15-3. Mode LIN UART The LIN configuration is independent of the programmed LIN protocol. The listening ...
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When the busy signal is set, some registers are locked, user writing is not allowed: • “LIN Control Register” - LINCR - except LCMD[2..0], LENA & LSWRES, • “LIN Baud Rate Registers” - LINBRRL & LINBRRH, • “LIN Data Length ...
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The re-synchronization implemented in the controller tolerates a clock deviation of ± 20% and adjusts the baud rate in a ± 2% range. The new LBT[5..0] value will be used up to the end of the response. Then, the LBT[5..0] ...
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Data Length in LIN 1.3 • LRXDL and LTXDL fields are both hardware updated before setting LIDOK by decoding the data length code contained in the received PROTECTED IDENTIFIER (LRXDL = LTXDL). • Via the above mechanism, a length ...
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If an error occurs, Tx stops, the corresponding error flag is set and LRXDL will give the number of transmitted bytes without error, • error occurs, LTXOK is set after the transmission of the CHECKSUM, LTXDL will ...
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Flags LERR bit of the LINSIR register is an logical ‘OR’ of all the bits of LINERR register (see tion 15.5.13 “Interrupts” on page • LBERR = LIN Bit ERRor. A unit that is sending a bit on ...
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Frame Time Out According to the LIN protocol, a frame time-out error is flagged if: T This feature is implemented in the LIN/UART controller. Figure 15-12. LIN timing and frame time-out T Header BREAK SYNC Field T T Header_Nominal ...
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CHECKSUM Frame identifiers 60 (0x3C (0x3D) shall always use classic checksum. 15.5.13 Interrupts As shown in are combined to drive two interrupts. Each of these flags have their respective enable interrupt bit in LINENIR register. (see 176). Figure ...
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The LIN protocol says that a message with an identifier from 60 (0x3C (0x3F) uses a classic checksum (sum over the data bytes only). Software will be responsible for switching correctly the LIN13 bit to provide/check this ...
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LIN / UART Register Description Table 15-5. LIN/UART Register Bits Summary Name Bit 7 Bit 6 LSWRES LIN13 LINCR 0 R/W 0 LIDST2 LIDST1 LINSIR — — LINENIR LABORT LTOERR LINERR 0 R ...
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LIN Control Register - LINCR Read/Write Initial Value • Bit 7 - LSWRES: Software Reset • Bit 6 - LIN13: LIN 1.3 mode • Bit 5:4 - LCONF[1:0]: Configuration • Bit 3 - LENA: Enable • Bit 2:0 - ...
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LIN Status and Interrupt Register - LINSIR Read/Write Initial Value • Bits 7:5 - LIDST[2:0]: Identifier Status • Bit 4 - LBUSY: Busy Signal • Bit 3 - LERR: Error Interrupt enable bit - LENERR - is set in ...
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Bit 0 - LRXOK: Receive Performed Interrupt LINENIR. 15.6.3 LIN Enable Interrupt Register - LINENIR Read/Write Initial Value • Bits 7:4 - Reserved Bits These bits are reserved for future use. For compatibility with future devices, they must be ...
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Bit 6 - LTOERR: Frame_Time_Out Error Flag • Bit 5 - LOVERR: Overrun Error Flag • Bit 4 - LFERR: Framing Error Flag • Bit 3 - LSERR: Synchronization Error Flag • Bit 2 - LPERR: Parity Error Flag ...
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Bits 5:0 - LBT[5:0]: LIN Bit Timing 15.6.6 LIN Baud Rate Register - LINBRR Read/Write Initial Value • Bits 15:12 - Reserved Bits These bits are reserved for future use. For compatibility with future devices, they must be written ...
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LIN Identifier Register - LINIDR Read/Write Initial Value • Bits 7:6 - LP[1:0]: Parity • Bits 5:4 - LDL[1:0]: LIN 1.3 Data Length • Bits 3:0 - LID[3:0]: LIN 1.3 Identifier • Bits 5:0 - LID[5:0]: LIN 2.1 Identifier ...
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Bit 3 - LAINC: Auto Increment of Data Buffer Index • Bits 2:0 - LINDX 2:0: FIFO LIN Data Buffer Index The FIFO data buffer is accessed through LINDAT. 15.6.10 LIN Data Register - LINDAT Read/Write Initial Value • ...
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ISRC - Current Source 16.1 Features • 100µA Constant current source • ±10% Absolute Accuracy The ATtiny87/167 features a 100µA ±10% Current Source request, the current is flow- ing through an external resistor. The voltage can be ...
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In automotive applications, distributed voltages are very disturbed. The internal Current Source solution of ATtiny87/167 immunizes the address detection the against any kind of volt- age variations. Table 16-1. Physical Address Table 16-2. Physical Address Note: 7728G–AVR–06/10 Example of Resistor ...
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Current Source for Low Cost Transducer An external transducer based on a variable resistor can be connected to the Current Source. This can be, for instance: • A thermistor, or temperature-sensitive resistor, used as a temperature sensor, • A ...
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ADC – Analog to Digital Converter 17.1 Features • 10-bit Resolution • 1.0 LSB Integral Non-linearity • ± 2 LSB Absolute Accuracy • 260 µs Conversion Time (Low - High Resolution) • kSPS at ...
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Figure 17-1. Analog to Digital Converter Block Schematic ATtiny87/ATtiny167 192 8-Bit Data Bus Analog Misc. ADC Multiplexer (AMISCR) Register A & B (ADCSRA/ADCSRB) Select (ADMUX) Internal 2.56 / 1.1V Reference AVCC AGND / AVCC 4 Bandgap Reference Temperature Sensor ADC10 ...
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Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approx- imation. The minimum value represents AGND and the maximum value represents the voltage on AVcc, the voltage refrence on AREF pin or an ...
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Starting a Conversion A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays high as long as the conversion is in progress and will be cleared by hardware when ...
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Prescaling and Conversion Timing Figure 17-3. ADC Prescaler By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution lower resolution than 10 bits is needed, the ...
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Figure 17-4. ADC Timing Diagram, First Conversion (Single Conversion Mode) ycle Number DC Clock DEN DSC DIF DCH DCL Figure 17-5. ADC Timing Diagram, Single Conversion ycle Number DC Clock DSC DIF DCH DCL Figure 17-6. ADC Timing Diagram, Auto ...
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Figure 17-7. ADC Timing Diagram, Free Running Conversion ycle Number DC Clock DSC DIF DCH DCL Conversion Table 17-1. Condition First conversion Normal conversions Auto Triggered conversions 17.6 Changing Channel or Reference Selection The MUX[4:0] and REFS[1:0] bits in the ...
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ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be ...
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The ADC is optimized for analog signals with an output impedance of approximately less. If such a source is used, the sampling time will be negligible source with higher impedance is used, the sampling time ...
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Figure 17-9. Offset Error • Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB ...