ATtiny167 Automotive Atmel Corporation, ATtiny167 Automotive Datasheet - Page 168

• Manufacturer Part Number: ATtiny167 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATtiny167 Automotive

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.4.6.2
15.4.6.3
168
ATtiny87/ATtiny167
Tx Header Function
Rx & TX Response Functions
In accordance with the LIN protocol, only the master task must enable this function. The
header is sent in the appropriate timed slots at the programmed baud rate (c.f. LINBRR & LIN-
BTR registers).
The controller is responsible for:
At the end of this transmission, the controller automatically returns to Rx Header / LIN Abort
state (i.e. LCMD[1..0] = 00) after setting the appropriate flags. This function leaves the control-
ler in the same setting as after the Rx Header function. This means that, in LIN 1.3, the
LINDLR register is set with the uncoded length value at the end of the Tx Header function.
During this function, the controller is also responsible for:
These functions are initiated by the slave task of a LIN node. They must be used after sending
an header (master task) or after receiving an header (considered as belonging to the slave
task). When the TX Response order is sent, the transmission begins. A Rx Response order
can be sent up to the reception of the last serial bit of the first byte (before the stop-bit).
In LIN 1.3, the header slot configures the LINDLR register. In LIN 2.1, the user must configure
the LINDLR register, either LRXDL[3..0] for Rx Response either LTXDL[3..0] for Tx Response.
When the command starts, the controller checks the LIN13 bit of the LINCR register to apply
the right rule for computing the checksum. Checksum calculation over the DATA bytes and the
PROTECTED IDENTIFIER byte is called enhanced checksum and it is used for communica-
tion with LIN 2.1 slaves. Checksum calculation over the DATA bytes only is called classic
checksum and it is used for communication with LIN 1.3 slaves. Note that identifiers 60 (0x3C)
to 63 (0x3F) shall always use classic checksum.
At the end of this reception or transmission, the controller automatically returns to Rx Header /
LIN Abort state (i.e. LCMD[1..0] = 00) after setting the appropriate flags.
If an LIN error occurs, the reception or the transmission is stopped, the appropriate flags are
set and the LIN bus is left to recessive state.
During these functions, the controller is responsible for:
While the controller is sending or receiving a response, BREAK and SYNCH fields can be
detected and the identifier of this new header will be recorded. Of course, specific errors on
the previous response will be maintained with this identifier reception.
• The transmission of the BREAK field - 13 dominant bits,
• The transmission of the SYNCH field - character 0x55,
• The transmission of the PROTECTED IDENTIFIER field. It is the full content of the LINIDR
• The starting of the Frame_Time_Out,
• The checking of the LIN communication integrity.
• The initialization of the checksum operator,
• The transmission or the reception of ‘
• The transmission or the checking of the CHECKSUM field,
• The checking of the Frame_Time_Out,
• The checking of the LIN communication integrity.
register (automatic check bits included).
n
’ data with the update of the checksum calculation,
7728G–AVR–06/10