ATtiny88 Atmel Corporation, ATtiny88 Datasheet - Page 156

• Manufacturer Part Number: ATtiny88
• Manufacturer: Atmel Corporation

Specifications of ATtiny88

• Flash (kbytes): 8 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

15.10 Compatibility with SMBus
15.11 Register Description
15.11.1
15.11.2
156
ATtiny48/88
TWBR – TWI Bit Rate Register
TWCR – TWI Control Register
As with any other I
should be aware of before connecting a TWI device to SMBus devices. For use in SMBus envi-
ronments, the following should be noted:
• Bits 7:0 – TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency
divider which generates the SCL clock frequency in the Master modes. See
Unit” on page 135
If the TWI operates in Master mode TWBR must be set to 10, or higher.
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a
Master access by applying a START condition to the bus, to generate a Receiver acknowledge,
to generate a stop condition, and to control halting of the bus while the data to be written to the
bus are written to the TWDR. It also indicates a write collision if data is attempted written to
TWDR while the register is inaccessible.
• Bit 7 – TWINT: TWI Interrupt Flag
This bit is set by hardware when the TWI has finished its current job and expects application
software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the
TWI Interrupt Vector. While the TWINT Flag is set, the SCL low period is stretched. The TWINT
Flag must be cleared by software by writing a logic one to it. Note that this flag is not automati-
cally cleared by hardware when executing the interrupt routine. Also note that clearing this flag
Bit
(0xB8)
Read/Write
Initial Value
Bit
(0xBC)
Read/Write
Initial Value
• All I/O pins of an AVR, including those of the two-wire interface, have protection diodes to
• The data hold time of the TWI is lower than specified for SMBus.
• SMBus has a low speed limit, while I
both supply voltage and ground. See
requirements of the SMBus specifications. As a result, supply voltage mustn’t be removed
from the AVR or the protection diodes will pull the bus lines down. Power down and sleep
modes is not a problem, provided supply voltages remain.
AVR must make sure bus speed does not drop below specifications, since lower bus speeds
trigger timeouts in SMBus slaves. If the AVR is configured a slave there is a possibility of a
bus lockup, since the TWI module doesn't identify timeouts.
TWBR7
TWINT
R/W
R/W
7
0
7
0
for calculating bit rates.
2
C-compliant interface there are known compatibility issues the designer
TWBR6
TWEA
R/W
R/W
6
0
6
0
TWBR5
TWSTA
R/W
R/W
5
0
5
0
2
Figure 10-1 on page
C hasn’t. As a master in an SMBus environment, the
TWBR4
TWSTO
R/W
R/W
4
0
4
0
TWBR3
TWWC
R/W
R
3
0
3
0
TWBR2
TWEN
R/W
R/W
60. This is in contradiction to the
2
0
2
0
TWBR1
R/W
R
1
0
1
–
0
“Bit Rate Generator
TWBR0
TWIE
R/W
R/W
0
0
0
0
8008H–AVR–04/11
TWBR
TWCR