ATtiny88 Atmel Corporation, ATtiny88 Datasheet - Page 99

• Manufacturer Part Number: ATtiny88
• Manufacturer: Atmel Corporation

Specifications of ATtiny88

• Flash (kbytes): 8 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

12.8
8008H–AVR–04/11
Compare Match Output Unit
The Compare Output mode (COM1x[1:0]) bits have two functions. The Waveform Generator
uses the COM1x[1:0] bits for defining the Output Compare (OC1x) state at the next compare
match. Secondly the COM1x[1:0] bits control the OC1x pin output source.
simplified schematic of the logic affected by the COM1x[1:0] bit setting. The I/O Registers, I/O
bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control
Registers (DDR and PORT) that are affected by the COM1x[1:0] bits are shown. When referring
to the OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a system
reset occur, the OC1x Register is reset to “0”.
Figure 12-5. Compare Match Output Unit (non-PWM Mode), Schematic
The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform
Generator if either of the COM1x[1:0] bits are set. However, the OC1x pin direction (input or out-
put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visi-
ble on the pin. The port override function is generally independent of the Waveform Generation
mode, but there are some exceptions. Refer to
details.
The design of the Output Compare pin logic allows initialization of the OC1x state before the out-
put is enabled. Note that some COM1x[1:0] bit settings are reserved for certain modes of
operation.
The COM1x[1:0] bits have no effect on the Input Capture unit.
COMnx1
COMnx0
FOCnx
clk
I/O
See “Register Description” on page 110.
Waveform
Generator
D
D
D
PORT
DDR
OCnx
Q
Q
Q
Table
12-2,
Table 12-3
1
0
ATtiny48/88
Figure 12-5
and
Table 12-4
OCnx
shows a
Pin
for
99