ATtiny88 Atmel Corporation, ATtiny88 Datasheet - Page 169

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ATtiny88

Manufacturer Part Number
ATtiny88
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATtiny88

Flash (kbytes)
8 Kbytes
Pin Count
32
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
28
Ext Interrupts
28
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes

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8008H–AVR–04/11
When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in
Figure
mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger
source signal. Three additional CPU clock cycles are used for synchronization logic.
Figure 17-6. ADC Timing Diagram, Auto Triggered Conversion
In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high. See
Figure 17-7. ADC Timing Diagram, Free Running Conversion
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
17-6. This assures a fixed delay from the trigger event to the start of conversion. In this
Prescaler
Reset
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
MUX and REFS
Update
1
Conversion
Complete
2
One Conversion
12
3
Sample &
Hold
4
13
Figure
5
14
6
17-7.
7
One Conversion
Next Conversion
1
Sign and MSB of Result
LSB of Result
8
9
2
MUX and REFS
Update
10
Conversion
Complete
3
11
Sample & Hold
12
4
ATtiny48/88
13
Sign and MSB of Result
LSB of Result
Next Conversion
1
Prescaler
Reset
2
169

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