ATtiny88 Atmel Corporation, ATtiny88 Datasheet - Page 80

• Manufacturer Part Number: ATtiny88
• Manufacturer: Atmel Corporation

Specifications of ATtiny88

• Flash (kbytes): 8 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

11. 8-bit Timer/Counter0
11.1
11.2
11.2.1
80
Features
Overview
ATtiny48/88
Definitions
•
•
•
Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output
Compare Units. It allows accurate program execution timing (event management). A simplified
block diagram of the 8-bit Timer/Counter is shown in
I/O pins, refer to
bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed
in the
The PRTIM0 bit in
enable Timer/Counter0 module.
Figure 11-1. 8-bit Timer/Counter Block Diagram
Many register and bit references in this section are written in general form, where a lower case
“n” replaces the Timer/Counter number (in this case 0) and a lower case “x” replaces the Output
Compare Unit (in this case Compare Unit A or Compare Unit B). However, when using the regis-
Two Independent Output Compare Units
Clear Timer on Compare Match (Auto Reload)
Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)
“8-bit Timer/Counter Register Description” on page
Timer/Counter
“Pinout of ATtiny48/88” on page
TCCRnA
OCRnA
TCNTn
OCRnB
“PRR – Power Reduction Register” on page 40
=
=
Count
Clear
Control Logic
TOP
=
Value
Fixed
TOP
2. CPU accessible I/O Registers, including I/O
clk
Tn
Figure
85.
11-1. For the actual placement of
TOVn
(Int.Req.)
Clock Select
OCnA (Int. Req.)
OCnB (Int. Req.)
( From Prescaler )
Detector
must be written to zero to
Edge
8008H–AVR–04/11
Tn