ATtiny88 Atmel Corporation, ATtiny88 Datasheet - Page 82

• Manufacturer Part Number: ATtiny88
• Manufacturer: Atmel Corporation

Specifications of ATtiny88

• Flash (kbytes): 8 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

11.5
11.5.1
82
Output Compare Unit
ATtiny48/88
Compare Match Blocking by TCNT0 Write
Signal description (internal signals):
Depending of the mode of operation used, the counter is cleared or incremented at each timer
clock (clk
Clock Select bits (CS0[2:0]). When no clock source is selected (CS0[2:0] = 0) the timer is
stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clk
is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the Clear Timer on Compare Match bit
(CTC0) located in the Timer/Counter Control Register (TCCR0A). For more details about
advanced counting sequences, see
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by
the CTC0 bit. TOV0 can be used for generating a CPU interrupt.
The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers
(OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a
match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock
cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output
Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is exe-
cuted. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit
location.
Figure 11-3
Figure 11-3. Output Compare Unit, Block Diagram
All CPU write operations to the TCNT0 Register will block any compare match that occur in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initial-
count
clear
clk
top
Tn
T0
). clk
shows a block diagram of the Output Compare unit.
T0
can be generated from an external or internal clock source, selected by the
OCRnx
Increment or decrement TCNT0 by 1.
Clear TCNT0 (set all bits to zero).
Timer/Counter clock, referred to as clk
Signalize that TCNT0 has reached maximum value.
“Modes of Operation” on page
=
OCFnx (Int.Req.)
(8-bit Comparator )
DATA BUS
83.
TCNTn
T0
in the following.
8008H–AVR–04/11
T0