ATxmega32A4 Atmel Corporation, ATxmega32A4 Datasheet - Page 214

• Manufacturer Part Number: ATxmega32A4
• Manufacturer: Atmel Corporation

Specifications of ATxmega32A4

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Speed: No
• Usb Interface: No
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.5.1
19.5.1.1
19.5.1.2
19.5.1.3
19.5.1.4
19.5.2
19.5.3
8077H–AVR–12/09
Transmitting Address Packets
Transmitting Data Packets
Receiving Data Packets
Case M1: Arbitration lost or bus error during address packet
Case M2: Address packet transmit complete - Address not acknowledged by slave
Case M3: Address packet transmit complete - Direction bit cleared
Case M4: Address packet transmit complete - Direction bit set
After issuing a START condition, the master starts performing a bus transaction when the mas-
ter Address register is written with the slave address and direction bit. If the bus is busy the TWI
master will wait until the bus becomes idle. When the bus is idle the master will issue a START
condition on the bus before the address byte is transmitted.
Depending on arbitration and the R/W direction bit one of four distinct cases (1 to 4) arises fol-
lowing the address packet. The different cases must be handled in software.
If arbitration is lost during the sending of the address packet the master Write Interrupt Flag and
Arbitration Lost flag are both set. Serial data output to the SDA line is disabled and the SCL line
is released. The master is no longer allowed to perform any operation on the bus until the bus
state has changed back to idle.
A bus error will behave in the same way as an arbitration lost condition, but the Error flag is set
in addition to Write Interrupt Flag and Arbitration Lost flag.
If no slave device responds to the address the master Write Interrupt Flag is set and the master
Received Acknowledge flag is set. The clock hold is active at this point preventing further activity
on the bus.
If the master receives an ACK from the slave, the master Write Interrupt Flag is set, and the
master Received Acknowledge flag is cleared. The clock hold is active at this point preventing
further activity on the bus.
If the master receives an ACK from the slave, the master proceeds receiving the next byte of
data from the slave. When the first data byte is received the master Read Interrupt Flag is set
and the master Received Acknowledge flag is cleared. The clock hold is active at this point pre-
venting further activity on the bus.
Assuming case 3 above, the master can start transmitting data by writing to the master Data reg-
ister. If the transfer was successful the slave will signal with ACK. The master Write Interrupt
Flag is set, the master Received Acknowledge flag is cleared and the master can prepare new
data to send. During data transfer the master is continuously monitoring the bus for collisions.
The Received Acknowledge flag must be checked for each data packet transmitted before the
next data packet can be transferred. The master is not allowed to continue transmitting data if
the slave signals a NACK.
If a collision is detected and the master looses arbitration during transfer, the Arbitration Lost
flag is set.
Assuming case 4 above the master has already received one byte from the slave. The master
Read Interrupt Flag is set, and the master must prepare to receive new data. The master must
respond to each byte with ACK or NACK. Indicating a NACK might not be successfully executed
XMEGA A
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