ATxmega32A4 Atmel Corporation, ATxmega32A4 Datasheet - Page 322

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ATxmega32A4

Manufacturer Part Number
ATxmega32A4
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega32A4

Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
7
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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26.10.4
26.10.5
8077H–AVR–12/09
EVCTRL – DAC Event Control Register
TIMCTRL – DAC Timing Control Register
• Bit 0 - LEFTADJ: DAC Left-Adjust Value
If this bit is set, CH0DATA and CH1DATA are left-adjusted.
• Bits 7:3 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bits 2:1 - EVSEL[2:0]: DAC Event Channel Input Selection
These bits define which channel from the Event System that is used for triggering a DAC
conversion.
Table 26-3
Table 26-3.
• Bit 7 - Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bits 6:4 - [2:0]: - CONINTVAL - DAC Conversion Interval
These bits control the minimum interval between two successive conversions. The interval must
be set relative to the Peripheral clock (clk
the result from the previous conversion has settled. The DAC Conversion Interval should never
be set lower than 1 µs during single channel operation, and not lower than 1.5 µs during dual
channel (S/H) operation.
Bit
+0x04
Read/Write
Initial Value
Bit
+0x03
Read/Write
Initial Value
EVSEL[2:0]
000
001
010
011
100
101
110
111
shows the available selections.
R
7
0
R
-
7
0
-
DAC Event input Selection
R/W
6
1
R
6
0
-
Group Configuration
CONINTVAL[2:0]
R/W
R
5
1
5
0
-
0
1
2
3
4
5
6
7
PER
R/W
R
4
0
4
0
-
) to ensure that a new conversion is not started until
Description
Event channel 0 as input to DAC
Event channel 1 as input to DAC
Event channel 2 as input to DAC
Event channel 3 as input to DAC
Event channel 4 as input to DAC
Event channel 5 as input to DAC
Event channel 6 as input to DAC
Event channel 7 as input to DAC
R/W
R
3
0
3
0
-
R/W
R/W
2
0
2
0
REFRESH[3:0]
EVSEL[2:0]
R/W
R/W
1
0
1
0
XMEGA A
R/W
R/W
0
0
0
1
TIMCTRL
EVCTRL
322

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