ATxmega32A4 Atmel Corporation, ATxmega32A4 Datasheet - Page 52
ATxmega32A4
Manufacturer Part Number
ATxmega32A4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32A4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
7
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- Current page: 52 of 445
- Download datasheet (6Mb)
5.9
5.10
5.11
5.12
8077H–AVR–12/09
Error detection
Software Reset
Protection
Interrupts
The DMA controller can detect erroneous operation. Error conditions are detected individually
for each DMA channel, and the error conditions are:
Both the DMA controller and a DMA channel can be reset from the user software. When the
DMA controller is reset, all registers associated with the DMA controller is cleared. A software
reset can only be done when the DMA controller is disabled. When a DMA channel is reset, all
registers associated with the DMA channel are cleared. A software reset can only be done when
the DMA channel is disabled.
In order to insure safe operation some of the channel registers are protected during a transac-
tion. When the DMA channel Busy flag (CHnBUSY) is set for a channel, the user can only
modify these registers and bits:
The DMA Controller can generate interrupts when an error is detected on a DMA channel or
when a transaction is complete for a DMA channel. Each DMA channel has a separate interrupt
vector, and there are different interrupt flags for error and transaction complete.
If repeat is not enabled the transaction complete flag is set at the end of the Block Transfer. If
unlimited repeat is enabled, the transaction complete flag is also set at the end of each Block
Transfer.
• Write to memory mapped EEPROM memory locations.
• Reading EEPROM memory when the EEPROM is off (sleep entered).
• DMA controller or a busy channel is disabled in software during a transfer.
• CTRL register
• INTFLAGS register
• TEMP registers
• CHEN, CHRST, TRFREQ, REPEAT bits of the Channel CTRL register
• TRIGSRC register
XMEGA A
52
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