ATxmega32A4 Atmel Corporation, ATxmega32A4 Datasheet - Page 283

• Manufacturer Part Number: ATxmega32A4
• Manufacturer: Atmel Corporation

Specifications of ATxmega32A4

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Speed: No
• Usb Interface: No
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.11.6
8077H–AVR–12/09
SDRAMCTRLC - SDRAM Control Register C
• Bit 7:6 - WRDLY[1:0]: SDRAM Write Recovery Delay
These bits select the Write Recovery time in number of Peripheral 2x clock (CLK
according to
Table 24-14. SDRAM Write Recovery Delay settings
• Bit 5:3 - ESRDLY[2:0]: SDRAM Exit Self Refresh to Active Delay
This field defines the delay between CKE set high and an Activate command in a number of
Peripheral 2x clock (CLK
Table 24-15. SDRAM Exit Self Refresh Delay settings
• Bit 2:0 - ROWCOLDLY[2:0]: SDRAM Row to Column Delay
This field defines the delay between an Activate command and a Read/Write command as a
number of Peripheral 2x clock (CLK
Table 24-16. SDRAM Row Column Delay settings
Bit
+0x09
Read/Write
Initial Value
ROWCOLDLY[2:0]
ESRDLY[2:0]
WRDLY[1:0]
000
001
010
011
100
101
110
111
000
001
010
011
00
01
10
11
Table 24-11 on page
R/W
7
0
WRDLY[1:0]
R/W
6
0
Group Configuration
0CLK
1CLK
2CLK
3CLK
Group Configuration
0CLK
1CLK
2CLK
3CLK
4CLK
5CLK
6CLK
7CLK
Group Configuration
0CLK
1CLK
2CLK
3CLK
PER2
) cycles, according to
R/W
5
0
282.
PER2
ESRDLY[1:0]
R/W
) cycles, according to
4
0
Description
0 CLK
1 CLK
2 CLK
3 CLK
Description
0 CLK
1 CLK
2 CLK
3 CLK
4 CLK
5 CLK
6 CLK
7 CLK
Description
0 CLK
1 CLK
2 CLK
3 CLK
R/W
3
0
Table 24-15 on page
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
R/W
2
0
ROWCOLDLY[1:0]
Table 24-16 on page
R/W
1
0
283.
R/W
0
0
XMEGA A
SDRAMCTRLC
PER2
283.
) cycles,
283