ATxmega64A3U Atmel Corporation, ATxmega64A3U Datasheet - Page 195

• Manufacturer Part Number: ATxmega64A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3U

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.10 Register Description
15.10.1
15.10.2
8331A–AVR–07/11
CTRLA — Control Register A
CTRLB — Control Register B
• Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:0 – CLKSEL[3:0]: Clock Select
These bits select clock source for the Timer/Counter according to
clock select is identical for both high and low byte timer/counter.
Table 15-2.
• Bit 7:0 – CMPHENx/CMPLENx: Compare High/Low Byte Enable x
Setting these bits will enable the compare output and override the port output register for the
corresponding OCn output pin.
Bit
+0x01
Read/Write
Initial Value
Bit
+0x00
Read/Write
Initial Value
CLKSEL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
CMPHEND
R/W
Clock Select
7
0
R
7
–
0
Group Configuration
OFF
DIV1
DIV2
DIV4
DIV8
DIV64
DIV256
DIV1024
EVCHn
CMPHENC
R/W
R
6
0
6
–
0
CMPHENB
R/W
R
5
0
5
–
0
CMPHENA
R/W
R
4
0
4
–
0
Description
None (i.e, Timer/Counter in ‘OFF’ state)
Prescaler: Clk
Prescaler: Clk
Prescaler: Clk
Prescaler: Clk
Prescaler: Clk
Prescaler: Clk
Prescaler: Clk
Event channel n, n= [0,...,7]
CMPLEND
Atmel AVR XMEGA AU
R/W
R/W
3
0
3
0
PER
PER
PER
PER
PER
PER
PER
CMPLENC
/2
/4
/8
/64
/256
/1024
R/W
R/W
2
0
2
0
CLKSEL[3:0]
Table 15-2 on page
CMPLENB
R/W
R/W
1
0
1
0
CMPLENA
R/W
R/W
0
0
0
0
195. The
CTRLA
CTRLB
195