ATxmega64A3U Atmel Corporation, ATxmega64A3U Datasheet - Page 433

• Manufacturer Part Number: ATxmega64A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3U

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

33.11.2
8331A–AVR–07/11
NVM Flash Commands
For Flash read operations (ELPM and LPM), one byte is read at a time. For this, the Least Sig-
nificant Bit (bit 0) in the Z-pointer is used to select the low byte or high byte in the word address.
If this bit is 0, the low byte is read, and if this bit is 1 the high byte is read.
The size of FWORD and FPAGE will depend on the page and flash size in the device, refer to
each device’s datasheet.
Once a programming operation is initiated, the address is latched and the Z-pointer can be
updated and used for other operations.
Figure 33-1. Flash addressing for self-programming
The NVM commands that can be used for accessing the Flash Program Memory, Signature
Row and Calibration Row are listed in
For self-programming of the Flash, the Trigger for Action Triggered Commands is to set the
CMDEX bit in the NVM CTRLA register (CMDEX). The Read Triggered Commands are trig-
gered by executing the (E)LPM instruction (LPM). The Write Triggered Commands is triggered
by executing the SPM instruction (SPM).
The Change Protected column indicate if the trigger is protected by the Configuration Change
Protection (CCP) or not. This is a special sequence to write/execute the trigger during self-pro-
gramming, for more details refer to
14. CCP is not required for external programming. The two last columns show the address
pointer used for addressing, and the source/destination data register.
Section 33.11.1.1 on page 432
algorithm for each NVM operation.
FLASHEND
FPAGE
00
01
02
PROGRAM MEMORY
Z-Pointer
BIT
PAGE
WITHIN THE FLASH
P
PAGE ADDRESS
A
G
E
M
S
through
B
FPAGE
”CCP – Configuration Change Protection Register” on page
Table
Section 33.11.2.14 on page 438
33-2.
W
O
Atmel AVR XMEGA AU
R
D
FWORD
M
S
B
WORD ADDRESS
WITHIN A PAGE
INSTRUCTION WORD
1
0/1
0
PAGE
Low/High Byte select for (E)LPM
explain in details the
00
01
02
PAGEEND
FWORD
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