ATxmega64A3U Atmel Corporation, ATxmega64A3U Datasheet - Page 227

• Manufacturer Part Number: ATxmega64A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3U

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.3.6
19.3.7
19.3.8
19.3.9
8331A–AVR–07/11
CNT1 - Counter Register 1
CNT2 - Counter Register 2
CNT3 - Counter Register 3
PER0 - Period Register 0
an effect in the RTC32 domain. Write operations to the CNT register will be blocked if the SYN-
CBUSY flag is set.
The synchronization of the CNT register value from the RTC32 domain to the system clock
domain can be done by writing one to the SYNCCNT bit in the SYNCCTRL register. The
updated and synchronized CNT register value is available after eight peripheral clock cycles.
After writing to the high byte of the CNT register, the condition for setting OVFIF and COMPIF,
as well as the overflow and compare match wake-up condition, will be disabled for the following
two RTC32 clock cycles.
The PER0, PER1, PER2, and PER3 registers represent the 32-bit value, PER. PER is con-
stantly compared with the counter value (CNT). A compare match will set OVFIF in the
INTFLAGS register, and CNT will be set to zero in the next RTC32 clock cycle. OVFIF will be set
on the next count after match.
The PER register can be written only if the RTC32 is disabled and not currently synchronizing;
i.e., when both ENABLE and SYNCBUSY are zero.
Bit
+0x04
Read/Write
Initial Value
Bit
+0x05
Read/Write
Initial Value
Bit
+0x06
Read/Write
Initial Value
Bit
+0x07
Read/Write
Reset Value
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
CNT[23:16]
CNT[31:24]
CNT[15:8]
CNT[7:0]
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
Atmel AVR XMEGA AU
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
CNT0
CNT1
CNT2
CNT3
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