ATxmega64A3U Atmel Corporation, ATxmega64A3U Datasheet - Page 216

• Manufacturer Part Number: ATxmega64A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3U

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18.2.1
18.2.2
8331A–AVR–07/11
Clock Domains
Interrupts and Events
The RTC is asynchronous, operating from a different clock source independently of the main
system clock and its derivative clocks, such as the peripheral clock. For control and count regis-
ter updates, it will take a number of RTC clock and/or peripheral clock cycles before an updated
register value is available in a register or until a configuration change has effect on the RTC.
This synchronization time is described for each register.
The RTC can generate both interrupts and events. The RTC will give a compare interrupt and/or
event at the first count after the counter value equals the Compare register value. The RTC will
give an overflow interrupt request and/or event at the first count after the counter value equals
the Period register value. The overflow will also reset the counter value to zero.
Due to the asynchronous clock domain, events will be generated only for every third overflow or
compare match if the period register is zero. If the period register is one, events will be gener-
ated only for every second overflow or compare match. When the period register is equal to or
above two, events will trigger at every overflow or compare match, just as the interrupt request.
Atmel AVR XMEGA AU
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