ISL59444IB-T13 Intersil, ISL59444IB-T13 Datasheet
ISL59444IB-T13
Specifications of ISL59444IB-T13
Related parts for ISL59444IB-T13
ISL59444IB-T13 Summary of contents
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... Ordering Information PART PART NUMBER MARKING PACKAGE † ISL59444IB 59444IB † ISL59444IB-T7 59444IB † ISL59444IB-T13 59444IB † ISL59444IBZ 59444IBZ (Note) (Pb-free) † ISL59444IBZ-T13 59444IBZ (Note) (Pb-free) † ISL59444IBZ-T7 59444IBZ (Note) (Pb-free) † SO16 (0.150”) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets ...
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Absolute Maximum Ratings (T A Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Electrical Specifications V+ = +5V -5V, GND = 0V, T Unless Otherwise Specified (Continued) PARAMETER DESCRIPTION +SR Slew Rate -SR Slew Rate PSRR Power Supply Rejection Ratio ISO Channel Isolation SWITCHING CHARACTERISTICS V Channel-to-Channel Switching Glitch GLITCH HIZ ...
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Typical Performance Curves 200mV OUT P 7.2pF 5.5pF INCLUDES 1.6pF L -4 BOARD CAPACITANCE -5 0.001 0.01 FREQUENCY (GHz) FIGURE 1. SMALL ...
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Typical Performance Curves 0.2 0.1 0 -0.1 -0.2 -0 16.6pF L -0 23.6pF -0.5 OUT P 25Ω 28.6pF C INCLUDES 1.6pF L L -0.7 BOARD CAPACITANCE ...
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Typical Performance Curves S0 OUT 20ns/DIV FIGURE 13. CHANNEL TO CHANNEL SWITCHING GLITCH 23.6pF HIZ OUT 20ns/DIV FIGURE 15. HIZ SWITCHING GLITCH ...
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Typical Performance Curves JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.4 1.250W 1.2 1 0.8 0.6 0.4 0 AMBIENT TEMPERATURE (°C) FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Pin Descriptions EQUIVALENT PIN ...
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Pin Descriptions (Continued) EQUIVALENT PIN NUMBER PIN NAME CIRCUIT 1 V+ OUT V- CIRCUIT 3 AC Test Circuits ISL59444 50Ω 2pF 75Ω FIGURE 21A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD V FIGURE ...
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Application Circuits V IN 50Ω FIGURE 22A. SMALL SIGNAL 200mV V IN 50Ω FIGURE 22B. LARGE SIGNAL 1V Application Information General The ISL59444 is a 4:1 mux that is ideal as a matrix element in high performance switchers and routers. ...
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Latch State The latched control signals allow for synchronized channel switching. When LE1 is low the master control latch loads the next switching address (S0, S1), while the closed (assuming LE2 is the inverse of LE1) slave control latch maintains ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...