AD9269 Analog Devices, AD9269 Datasheet - Page 23

• Manufacturer Part Number: AD9269
• Description: 16-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9269

• Resolution (bits): 16bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

CLOCK
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 51. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516/AD9517
excellent jitter performance.
CLOCK
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 52. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517
clock drivers offer excellent jitter performance.
CLOCK
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK− pin to ground with a 0.1 μF capacitor (see
Figure 53).
Input Clock Divider
The AD9269 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 6.
Optimum performance is obtained by enabling the internal
duty cycle stabilizer (DCS) when using divide ratios other than
1, 2, or 4.
CLOCK
CLOCK
INPUT
INPUT
INPUT
INPUT
INPUT
Figure 53. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
50kΩ
50kΩ
Figure 51. Differential PECL Sample Clock (Up to 480 MHz)
Figure 52. Differential LVDS Sample Clock (Up to 480 MHz)
50Ω
1
50Ω RESISTOR IS OPTIONAL.
0.1µF
1
0.1µF
0.1µF
50kΩ
0.1µF
0.1µF
50kΩ
V
CC
1kΩ
1kΩ
PECL DRIVER
LVDS DRIVER
CMOS DRIVER
AD951x
AD951x
AD951x
240Ω
OPTIONAL
240Ω
100Ω
0.1µF
100Ω
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
clock drivers offer
0.1µF
CLK+
CLK–
CLK+
CLK–
CLK+
CLK–
ADC
ADC
ADC
Rev. 0 | Page 23 of 40
The AD9269 clock divider can be synchronized using the external
SYNC input. Bits[2:1] in Register 0x100 allow the clock divider
to be resynchronized on every SYNC signal or only on the first
SYNC signal after the register is written. A valid SYNC causes
the clock divider to reset to its initial state. This synchronization
feature allows multiple parts to have their clock dividers aligned
to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9269 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9269. Noise and distortion perform-
ance are nearly flat for a wide range of duty cycles with the DCS
on, as shown in Figure 54.
Jitter in the rising edge of the input is still of concern and is not
easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates of less than
20 MHz nominally. The loop has a time constant associated
with it that must be considered in applications in which the
clock rate can change dynamically. A wait time of 1.5 μs to 5 μs
is required after the dynamic clock frequency increases or decreases
before the DCS loop is relocked to the input signal.
80
79
78
77
76
75
74
73
72
71
70
30
Figure 54. SNR vs. Duty Cycle Stabilizer On/Off
35
40
POSITIVE DUTY CYCLE (%)
45
50
55
60
DCS OFF
DCS ON
65
AD9269
70