AD9269 Analog Devices, AD9269 Datasheet - Page 8

• Manufacturer Part Number: AD9269
• Description: 16-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9269

• Resolution (bits): 16bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9269
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled,
unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
DATA OUTPUT PARAMETERS
OUT-OF-RANGE RECOVERY TIME
1
2
Conversion rate is the clock rate after the CLK divider.
Wake-up time is dependent on the value of the decoupling capacitors.
Input Clock Rate
Conversion Rate
CLK Period—Divide-by-1 Mode (t
CLK Pulse Width High (t
Aperture Delay (t
Aperture Uncertainty (Jitter, t
Data Propagation Delay (t
DCO Propagation Delay (t
DCO to Data Skew (t
Pipeline Delay (Latency)
Wake-Up Time
Standby
With QEC Active
2
CH A/CH B DATA
CH A/CH B DATA
1
A
)
DCOA/DCOB
DCOA/DCOB
SKEW
CH
)
CLK+
CLK–
CLK+
CLK–
)
DCO
PD
VIN
VIN
)
)
J
)
CLK
)
N – 1
N – 1
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
t
t
CH
CH
Figure 3. CMOS Interleaved Output Timing
Min
3
50/25
AD9269-20/AD9269-40
Figure 2. CMOS Output Data Timing
t
t
PD
PD
N
N
t
t
t
t
CH A
N – 9
A
A
CLK
CLK
Typ
25.0/12.5
1.0
0.1
3
3
0.1
9
11
350
600/400
2
t
t
Rev. 0 | Page 8 of 40
DCO
DCO
t
t
SKEW
N – 9
SKEW
CH B
N – 9
N + 1
N + 1
CH A
N – 8
Max
480
20/40
N – 8
CH B
N – 8
N + 2
N + 2
Min
3
15.38
CH A
N – 7
N – 7
AD9269-65
N + 3
N + 3
CH B
N – 7
Typ
7.69
1.0
0.1
3
3
0.1
9
11
350
300
2
CH A
N – 6
N – 6
Max
480
65
N + 4
N + 4
CH B
N – 6
Min
3
12.5
CH A
N – 5
N – 5
AD9269-80
N + 5
N + 5
Typ
6.25
1.0
0.1
3
3
0.1
9
11
350
260
2
Max
480
80
Unit
MHz
MSPS
ns
ns
ns
ps rms
ns
ns
ns
Cycles
Cycles
μs
ns
Cycles