AD9265

Manufacturer Part NumberAD9265
Description16-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter
ManufacturerAnalog Devices
AD9265 datasheet
 

Specifications of AD9265

Resolution (bits)16bit# Chan1
Sample Rate125MSPSInterfaceLVDS,Par
Analog Input TypeDiff-UniAin Range(2Vref) p-p,1 V p-p,2 V p-p
Adc ArchitecturePipelinedPkg TypeCSP
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FEATURES
SNR = 79.0 dBFS @ 70 MHz and 125 MSPS
SFDR = 93 dBc @ 70 MHz and 125 MSPS
Low power: 373 mW @ 125 MSPS
1.8 V analog supply operation
1.8 V CMOS or LVDS output supply
Integer 1-to-8 input clock divider
IF sampling frequencies to 300 MHz
−154.3 dBm/Hz small signal input noise with 200 Ω input
impedance @ 70 MHz and 125 MSPS
Optional on-chip dither
Programmable internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
APPLICATIONS
Communications
Multimode digital receivers (3G)
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX,
and TD-SCDMA
Smart antenna systems
General-purpose software radios
Broadband data applications
Ultrasound equipment
SENSE
VREF
VCM
VIN+
VIN–
DITHER
CLK+
CLK–
SYNC
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
16-Bit, 125 MSPS/105 MSPS/80 MSPS,
1.8 V Analog-to-Digital Converter
PRODUCT HIGHLIGHTS
1.
On-chip dither option for improved SFDR performance
with low power analog input.
2.
Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 300 MHz.
3.
Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating 1.8 V CMOS or
LVDS outputs.
4.
Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock duty cycle stabilizer, DCS, power-down, test
modes, and voltage reference mode.
5.
Pin compatibility with the AD9255, allowing a simple
migration from 16 bits down to 14 bits.
FUNCTIONAL BLOCK DIAGRAM
RBIAS
PDWN
AGND
AVDD (1.8V)
REFERENCE
AD9265
TRACK-AND-HOLD
OUTPUT
ADC
STAGING
16
16-BIT
CMOS OR
CORE
LVDS
(DDR)
CLOCK
MANAGEMENT
SERIAL PORT
SVDD SCLK/
SDIO/
CSB
DFS
DCS
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
AD9265
LVDS LVDS_RS
DRVDD (1.8V)
16
D15 TO D0
OR
DCO
www.analog.com
©2009–2010 Analog Devices, Inc. All rights reserved.

AD9265 Summary of contents

  • Page 1

    ... CORE LVDS (DDR) CLOCK MANAGEMENT SERIAL PORT SVDD SCLK/ SDIO/ CSB DFS DCS Figure 1. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 AD9265 LVDS LVDS_RS DRVDD (1.8V) 16 D15 DCO www.analog.com ©2009–2010 Analog Devices, Inc. All rights reserved. ...

  • Page 2

    ... AD9265 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Product Highlights ........................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 ADC DC Specifications ............................................................... 4 ADC AC Specifications ................................................................. 5 Digital Specifications ................................................................... 6 Switching Specifications ................................................................ 8 Timing Specifications .................................................................. 9 Absolute Maximum Ratings .......................................................... 10 Thermal Characteristics ............................................................ 10 ESD Caution ................................................................................ 10 Pin Configurations and Function Descriptions ......................... 11 Typical Performance Characteristics ........................................... 15 Equivalent Circuits ......................................................................... 23 Theory of Operation ...

  • Page 3

    ... An optional on- chip dither function is available to improve SFDR performance with low power analog input signals. The AD9265 is available in a Pb-free, 48-lead LFCSP and is speci- fied over the industrial temperature range of −40°C to +85°C. Rev Page ...

  • Page 4

    ... Full 126 131 Full 14 Full 43 Full 241 258 Full 254 Full 308 Full 54 Full 0.05 0.15 Full Rev Page AD9265BCPZ-125 Typ Max Min Typ Max 16 Guaranteed Guaranteed ±0.05 ±0.25 ±0.05 ±0.25 ±0.2 ±2.5 ±0.4 ±2.5 +1.25 −1.0 +1.25 ±0.65 ±0.7 ±3.5 ±4.5 ±2.0 ± ...

  • Page 5

    ... Full 92 88 25°C 82 25°C 81 25°C 103 25°C 103 25°C 104 25°C 102 25°C 110 25°C 110 25°C 110 25°C 110 Rev Page AD9265 2 2 AD9265BCPZ-125 Typ Max Min Typ Max 79.7 79.0 79.2 79.0 77.3 78.3 77.5 76.9 75.6 79.4 78.7 78.8 78.7 77.0 77.5 77.0 75.7 74.4 12.9 12.8 12.8 12.8 12.6 12.5 12.3 12.1 −90 −88 − ...

  • Page 6

    ... Full Full 8 Full Full AGND Full 1.2 Full AGND Full −100 Full −100 Full Full 12 Rev Page AD9265BCPZ-125 Typ Max Min Typ Max −105 −101 −104 −103 −95 −92 −103 −104 −103 −100 −105 −102 −105 −103 −99 −98 − ...

  • Page 7

    ... Full Full Full Full Full Full Full Full Full 2 Full Full Full Full Full Full Full Full Full Full Full Full Full Full Rev Page AD9265 Min Typ Max Unit 1.22 SVDD V 0 0.6 V −10 +10 μA 40 132 μA 26 kΩ 1.22 SVDD V 0 ...

  • Page 8

    ... Full 1.0 Full 0.07 Full 2.4 2.8 3.4 2.4 Full 2.7 3.4 4.2 2.7 Full 0.3 0.6 0.9 0.3 Full 12 Full 2.6 3.4 4.2 2.6 Full 3.3 3.8 4.3 3.3 Full −0.3 0.4 1.2 −0.3 Full 12.5 Full 500 Full 2 Rev Page AD9265BCPZ-125 Typ Max Min Typ Max Unit 625 625 MHz 105 20 125 MSPS 105 10 125 MSPS 8 ns 4.75 6.65 2.4 4 5.6 ns 4.75 5.0 3.8 4 4.2 ns 0.8 ns 0.8 ns 1.0 1.0 ns 0.07 0.07 ps rms 2.8 3.4 2.4 2 ...

  • Page 9

    ... Figure 3. SYNC Input Timing Requirements Rev Page Min Typ 0.30 0. DEx DOx DEx DOx DEx DOx – 10 – 10 – 9 – 9 – 8 – – – – 8 AD9265 Max Unit ...

  • Page 10

    ... AD9265 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AVDD to AGND DRVDD to AGND SVDD to AGND VIN+, VIN− to AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND VCM to AGND RBIAS to AGND CSB to AGND SCLK/DFS to AGND SDIO/DCS to AGND OEB to AGND PDWN to AGND ...

  • Page 11

    ... CMOS Output Data. CMOS Output Data. CMOS Output Data. CMOS Output Data. CMOS Output Data. CMOS Output Data. CMOS Output Data. CMOS Output Data. Rev Page AVDD 35 DITHER 34 AVDD 33 SVDD 32 CSB 31 SCLK/DFS 30 SDIO/DCS 29 DRVDD 28 DNC D15 (MSB) 25 D14 AD9265 ...

  • Page 12

    ... AD9265 Pin No. Mnemonic Type 19 D9 Output 21 D10 Output 22 D11 Output 23 D12 Output 24 D13 Output 25 D14 Output 26 D15 (MSB) Output 27 OR Output 8 DCO Output SPI Control 31 SCLK/DFS Input 30 SDIO/DCS Input/output 32 CSB Input ADC Configuration 6 OEB Input 35 DITHER Input 41 LVDS_RS Input 44 LVDS Input ...

  • Page 13

    ... LVDS Output Data Bit 6/Bit 7—True. LVDS Output Data Bit 6/Bit 7—Complement. LVDS Output Data Bit 8/Bit 9 —True. LVDS Output Data Bit 8/Bit 9—Complement. Rev Page AVDD 35 DITHER 34 AVDD 33 SVDD 32 CSB 31 SCLK/DFS 30 SDIO/DCS 29 DRVDD 28 OR+ 27 OR– 26 D14/15+ 25 D14/15– AD9265 ...

  • Page 14

    ... AD9265 Pin No. Mnemonic Type 22 D10/11+ Output 21 D10/11− Output 24 D12/13+ Output 23 D12/13− Output 26 D14/15+ Output 25 D14/15− Output 28 OR+ Output 27 OR− Output 8 DCO+ Output 7 DCO− Output SPI Control 31 SCLK/DFS Input 30 SDIO/DCS Input/output 32 CSB Input ADC Configuration 6 OEB Input ...

  • Page 15

    ... MHz IN THIRD HARMONIC 70.1 MHz Figure 10. AD9265-80 Single-Tone FFT with f IN SECOND HARMONIC 30 40 Figure 11. AD9265-80 Single-Tone SNR/SFDR vs. Input Amplitude (A = 140.1 MHz IN Rev Page 80MSPS 200.3MHz @ –1dBFS SNR = 76.5dB (77.5dBFS) –20 SFDR = 81.2dBc –40 –60 –80 SECOND HARMONIC – ...

  • Page 16

    ... SNRFS (DITHER OFF) 80 SNRFS (DITHER ON) 70 –100 –90 –80 –70 –60 –50 –40 INPUT AMPLITUDE (dBFS) Figure 12. AD9265-80 Single-Tone SNR/SFDR vs. Input Amplitude ( MHz With and Without Dither Enabled IN 100 95 SFDR @ +85° SNR @ –40° SNR @ +25°C SNR @ +85°C ...

  • Page 17

    ... MHz Figure 22. AD9265-105 Single-Tone FFT with f IN 120 100 –100 40 50 Figure 23. AD9265-105 Single-Tone SNR/SFDR vs. Input Amplitude (A = 140.1 MHz Rev Page 105MSPS 200.3MHz @ –1dBFS SNR = 75.9dB (76.9dBFS) SFDR = 82dBc THIRD HARMONIC SECOND HARMONIC FREQUENCY (MHz) = 200 ...

  • Page 18

    ... SNRFS (DITHER OFF) 80 SNRFS (DITHER ON) 70 –100 –90 –80 –70 –60 –50 –40 INPUT AMPLITUDE (dBFS) Figure 24. AD9265-105 Single-Tone SNR/SFDR vs. Input Amplitude ( MHz with and without Dither Enabled IN 100 SFDR @ –40°C 95 SFDR @ +85° SNR @ –40° SNR @ +25°C SNR @ +85° ...

  • Page 19

    ... Figure 33. AD9265-125 Single-Tone FFT with –20 –40 –60 SECOND HARMONIC –80 –100 –120 –140 30.3 MHz Figure 34. AD9265-125 Single-Tone FFT with –20 –40 –60 –80 –100 –120 –140 70.1 MHz Figure 35. AD9265-125 Single-Tone FFT with f IN Rev Page 125MSPS 140.1MHz @ – ...

  • Page 20

    ... MHz @ −6 dBFS with Figure 39. AD9265-125 Single-Tone SNR/SFDR vs. Input Amplitude ( 70.1 MHz @ −23 dBFS with Figure 40. AD9265-125 Single-Tone SNR/SFDR vs. Input Amplitude ( 70.1 MHz @ −23 dBFS with Figure 41. AD9265-125 Single-Tone SNR/SFDR vs. Input Amplitude (A Rev Page 120 ...

  • Page 21

    ... IMD3 (dBc) –60 –80 SFDR (dBFS) –100 –120 IMD3 (dBFS) –140 –90 –78 –66 –54 –42 INPUT AMPLITUDE (dBFS) Figure 44. AD9265-125 Two-Tone SFDR/IMD3 vs. Input Amplitude (A with f = 29.1 MHz 32.1 MHz, f IN1 IN2 –20 –40 SFDR @ +85°C –60 –80 –100 –120 –140 250 300 Figure 45 ...

  • Page 22

    ... S 2.13 LSB RMS 50,000 60,000 = 9.7 MHz IN Rev Page 1.00 0.75 0.50 0. 10,000 20,000 30,000 40,000 50,000 OUTPUT CODE Figure 51. AD9265-125 DNL with f = 9.7 MHz IN 100 SFDR 90 SNR 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 INPUT COMMON-MODE VOLTAGE (V) Figure 52. AD9265-125 SNR/SFDR vs. Input Common Mode (VCM) with MHz IN 60,000 1.15 1.20 ...

  • Page 23

    ... Figure 57. Equivalent VREF Circuit SVDD CLK– SDIO/DCS Figure 58. Equivalent SDIO/DCS Circuit SCLK/DFS Figure 59. Equivalent SCLK/DFS Input Circuit CSB Figure 60. Equivalent CSB Input Circuit Rev Page AD9265 AVDD 6kΩ 26kΩ 350Ω SVDD 350Ω 26kΩ SVDD 26kΩ ...

  • Page 24

    ... AD9265 350Ω PDWN Figure 61. Equivalent PDWN Circuit DRVDD 350Ω OEB Figure 62. Equivalent OEB Input Circuit LVDS OR LVDS_RS 26kΩ Figure 63. Equivalent DITHER, LVDS, and LVDS_RS Input Circuit 26kΩ Rev Page AVDD DITHER, 350Ω 26kΩ ...

  • Page 25

    ... ADC core. The span of the ADC core is set by this buffer to 2 × VREF. Input Common Mode The analog inputs of the AD9265 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that V ...

  • Page 26

    ... AD8138, ADA4937-2, and excellent performance and a flexible interface to the ADC. The output common-mode voltage of the ADA4938 is easily set with the VCM pin of the AD9265 (see Figure 66), and the driver can be configured in the filter topology shown to provide band limiting of the input signal. ...

  • Page 27

    ... Nyquist zone and higher is to use the ADL5562 differential driver. The ADL5562 provides three selectable gain options up to 15.5 dB. An example circuit is shown in Figure 69; additional filtering between the ADL5562 output and the AD9265 input may be required to reduce out-of- band noise. See the C2 0.1µF R1 33Ω ...

  • Page 28

    ... The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference. 1.0µF If the internal reference of the AD9265 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 72 shows how the internal reference voltage is affected by loading ...

  • Page 29

    ... Jitter Considerations section. Figure 75 and Figure 76 show two preferred methods for clocking the AD9265. A low jitter clock source is converted from a single- ended signal to a differential signal using either an RF transformer balun. ...

  • Page 30

    ... Input Clock Divider CLK– The AD9265 contains an input clock divider with the ability to divide the input clock by integer values between 2 and 8. For clock divide ratios the duty cycle stabilizer (DCS) is not required because the output of the divider inherently produces a 50% duty cycle ...

  • Page 31

    ... ADCs. POWER DISSIPATION AND STANDBY MODE As shown in Figure 81, the power dissipated by the AD9265 is proportional to its sample rate. In CMOS output mode, the digital power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. ...

  • Page 32

    ... Minimize the length of the output data lines and loads placed on them to reduce transients within the AD9265. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the AD9265 is 10 MSPS. At clock rates below 10 MSPS, dynamic performance can degrade. Data Clock Output (DCO) ...

  • Page 33

    ... AD9265. BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9265 signal path. When enabled, the test runs from an internal pseudorandom noise (PN) source through the digital datapath starting at the ADC block output. The BIST sequence runs for 512 cycles and stops ...

  • Page 34

    ... If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9265 to prevent these signals from transi- tioning at the converter inputs during critical sampling periods. Some pins serve a dual function when the SPI interface is not being used ...

  • Page 35

    ... Table 16 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9265 part-specific features are described in detail following Table 17, the external memory map register table. Table 16. Features Accessible Using the SPI ...

  • Page 36

    ... Address 0x18). If the entire address location is open (for example, Address 0x13), this address location should not be written. Default Values After the AD9265 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 17. Logic Levels An explanation of logic level terminology follows:  ...

  • Page 37

    ... Test mode Open Open 0x0E BIST enable Open Open Bit 5 Bit 4 Bit 3 Bit 2 Soft reset 1 1 Soft reset 8-bit Chip ID[7:0], AD9265 = 0x64 (default) Speed grade ID Open Open 01 = 125 MSPS 10 = 105 MSPS MSPS Open Open Open Open External Open Open Open ...

  • Page 38

    ... AD9265 Addr. Register (Hex) Name Bit 7 (MSB) Bit 6 0x14 Output Drive Output mode strength type 0 = ANSI LVDS 0 = CMOS 1 = reduced 1 = LVDS LVDS 0x16 Clock phase Invert DCO Open control clock 0x17 DCO output Open Open delay 0x18 VREF select Reference voltage selection ...

  • Page 39

    ... Bit 1 is high and Bit 0 is high. This is continuous sync mode. Bit 0—Master Sync Enable Bit 0 must be high to enable any of the sync functions. If the sync capability is not used, this bit should remain low to conserve power. Rev Page AD9265 ...

  • Page 40

    ... Decouple the VCM pin to ground with a 0.1 μF capacitor, as shown in Figure 67. RBIAS The AD9265 requires that a 10 kΩ resistor be placed between the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance. ...

  • Page 41

    ... Temperature Range AD9265BCPZ-125 −40°C to +85°C AD9265BCPZRL7-125 −40°C to +85°C AD9265BCPZ-105 −40°C to +85°C AD9265BCPZRL7-105 −40°C to +85°C AD9265BCPZ-80 −40°C to +85°C AD9265BCPZRL7-80 −40°C to +85°C AD9265-125EBZ AD9265-105EBZ AD9265-80EBZ RoHS Compliant Part. 7.10 0.60 MAX 7.00 SQ 6.90 0.60 MAX 0.50 6.85 REF 6 ...

  • Page 42

    ... AD9265 NOTES Rev Page ...

  • Page 43

    ... NOTES Rev Page AD9265 ...

  • Page 44

    ... AD9265 NOTES ©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08502-0-1/10(A) Rev Page ...