AD9289 Analog Devices, AD9289 Datasheet - Page 15

• Manufacturer Part Number: AD9289
• Description: Quad 8-Bit, 65 MSPS, Serial LVDS A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9289

• Resolution (bits): 8bit
• # Chan: 4
• Sample Rate: 65MSPS
• Interface: Ser
• Analog Input Type: Diff-Uni
• Ain Range: 1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

An internal reference buffer creates the positive and negative
reference voltages, REFT and REFB, respectively, that defines
the span of the ADC core. The output common-mode of the
reference buffer is set to midsupply, and the REFT and REFB
voltages and span are defined as
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the midsupply voltage
and, by definition, the input span is twice the value of the VREF
voltage.
The internal voltage reference can be pin-strapped to fixed
values of 0.5 V or 1.0 V or adjusted within the same range, as
discussed in the Internal Reference Connection section.
Maximum SNR performance is achieved by setting the AD9289
to the largest input span of 2 V p-p.
The SHA should be driven from a source that keeps the signal
peaks within the allowable range for the selected reference
voltage. The minimum and maximum common-mode input
levels are defined in Figure 26 and Figure 27.
Differential Input Configurations
Optimum performance is achieved by driving the AD9289 in a
differential input configuration. For baseband applications, the
AD8351 differential driver provides excellent performance and
a flexible interface to the ADC (see Figure 28).
1V p-p
However, the noise performance of most amplifiers is not
adequate to achieve the true performance of the AD9289. For
applications where SNR is a key parameter, differential transfor-
mer coupling is the recommended input configuration. An
example of this is shown in Figure 29.
In any configuration, the value of the shunt capacitor, C, is
dependent on the input frequency and may need to be reduced
or removed.
REFT = 1/2 (AVDD + VREF)
REFB = 1/2 (AVDD − VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
Figure 28. Differential Input Configuration Using the AD8351
25Ω
50Ω
0.1µF
0.1µF
0.1µF
10Ω
10Ω
25Ω
1kΩ
1kΩ
GP1
GP2
V
CM
1.2kΩ
PWUP
AD8351
10kΩ
0.1µF
0.1µF
1kΩ
1kΩ
R
R
C
1kΩ
1kΩ
VIN–
VIN+
AD9289
AGND
AVDD
AVDD
Rev. 0 | Page 15 of 32
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, there is a
degradation in SFDR and distortion performance due to the
large input common-mode swing. However, if the source
impedances on each input are matched, there should be little
effect on SNR performance. Figure 30 details a typical single-
ended input configuration.
CLOCK INPUT AND CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result may be
sensitive to clock duty cycle. Typically, a 5% tolerance is
required on the clock duty cycle to maintain dynamic perfor-
mance characteristics. The AD9289 has a self-contained clock
duty cycle stabilizer that retimes the nonsampling edge,
providing an internal clock signal with a nominal 50% duty
cycle. This allows a wide range of clock input duty cycles
without affecting the performance of the AD9289.
An on-board phase-locked loop (PLL) multiplies the input
clock rate for the purpose of shifting the serial data out. As a
result, any change to the sampling frequency requires a
minimum of 100 clock periods to allow the PLL to reacquire
and lock to the new rate.
1kΩ
1kΩ
2V p-p
2V p-p
Figure 29. Differential Transformer-Coupled Configuration
AVDD
1kΩ
1kΩ
Figure 30. Single-Ended Input Configuration
AVDD
49.9Ω
49.9Ω
10µF
10µF
0.1µF
0.1µF
0.1µF
1kΩ
1kΩ
R
R
R
R
C
C
VIN+
VIN–
VIN+
VIN–
AD9289
AD9289
AGND
AGND
AVDD
AVDD
AD9289