AD9289 Analog Devices, AD9289 Datasheet - Page 16

• Manufacturer Part Number: AD9289
• Description: Quad 8-Bit, 65 MSPS, Serial LVDS A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9289

• Resolution (bits): 8bit
• # Chan: 4
• Sample Rate: 65MSPS
• Interface: Ser
• Analog Input Type: Diff-Uni
• Ain Range: 1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9289
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale
input frequency (f
calculated with the following equation:
In the equation, the rms aperture jitter, t
sum square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification.
Applications that require undersampling are particularly
sensitive to jitter.
The LVDS clock input should be treated as an analog signal in
cases where aperture jitter may affect the dynamic range of the
AD9289. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other
methods), it should be retimed by the original clock at the
last step.
The AD9289 can also support a single-ended CMOS clock.
Refer to the evaluation board schematics to enable this feature.
Power Dissipation and Standby Mode
As shown in Figure 31, the power dissipated by the AD9289 is
proportional to its sample rate. The digital power dissipation
does not vary because it is determined primarily by the strength
of the digital drivers and the load on each output bit.
Digital power consumption can be minimized by reducing the
capacitive load presented to the output drivers. The data in
Figure 31 was collected while a 5 pF load was placed on each
output driver.
The analog circuitry of the AD9289 is optimally biased to
achieve excellent performance while affording reduced
power consumption.
600
550
500
450
400
350
SNR degradation = 20 × log10 [1/2 × π × f
10
Figure 31. Supply Current vs. f
20
A
) due only to aperture jitter (t
30
ENCODE (MSPS)
40
I
I
AVDD
DRVDD
POWER
SAMPLE
50
for f
A
, represents the root
IN
60
= 10.3 MHz
A
× t
A
) can be
70
A
]
180
160
140
120
100
80
60
40
20
0
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By asserting the PDWN pin high, the AD9289 is placed in
standby mode. In this state, the ADC typically dissipates 7 mW.
During standby the LVDS output drivers are placed in a high
impedance state. Reasserting the PDWN pin low returns the
AD9289 into its normal operational mode.
In standby mode, low power dissipation is achieved by shutting
down the reference, reference buffer, and biasing networks. The
decoupling capacitors on REFT and REFB are discharged when
entering standby mode and then must be recharged when
returning to normal operation. As a result, the wake-up time is
related to the time spent in standby mode, and shorter standby
cycles result in proportionally shorter wake-up times. With the
recommended 0.1 µF and 10 µF decoupling capacitors on REFT
and REFB, it takes approximately 1 s to fully discharge the
reference buffer decoupling capacitors and 7 ms to restore full
operation.
Digital Outputs
The AD9289’s differential outputs conform to the ANSI-644
LVDS standard. To set the LVDS bias current place a resistor
(RSET is nominally equal to 3.9 kΩ) to ground at the
LVDSBIAS pin. The RSET resistor current is derived on-chip
and sets the output current at each output equal to a nominal
3.5 mA. A 100 Ω differential termination resistor placed at the
LVDS receiver inputs results in a nominal ±350 mV swing at
the receiver. To adjust the differential signal swing, simply
change the resistor to a different value, as shown in Table 7.
Table 7. LVDSBIAS Pin Configuration
RSET
3.6k
3.9k (Default)
4.3k
The AD9289’s LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capa-
bility for superior switching performance in noisy environ-
ments. Single point-to-point net topologies are recommended
with a 100 Ω termination resistor placed as close to the receiver
as possible. It is recommended to keep the trace length no
longer than 12 inches and to keep differential output traces
close together and at equal lengths.
The format of the output data can be selected as offset binary or
twos complement. A quick example of each output coding
format can be found in Table 8. The DFS pin is used to set the
format (see Table 9).
Table 8. Digital Output Coding
Code
255
128
127
0
VIN+ −
VIN− Input
Span = 2 V
p-p (V)
1.000
0
−0.00781
−1.00
VIN+ −
VIN− Input
Span = 1 V
p-p (V)
0.500
0
−0.00391
−0.5000
Differential Output Swing
375 mV p-p
350 mV p-p
325mV p-p
Digital
Output Offset
Binary
(D7...D0)
1111 1111
1000 0000
0111 1111
0000 0000
Digital
Output Twos
Complement
(D7...D0)
0111 1111
0000 0000
1111 1111
1000 0000