AD9289 Analog Devices, AD9289 Datasheet - Page 4

• Manufacturer Part Number: AD9289
• Description: Quad 8-Bit, 65 MSPS, Serial LVDS A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9289

• Resolution (bits): 8bit
• # Chan: 4
• Sample Rate: 65MSPS
• Interface: Ser
• Analog Input Type: Diff-Uni
• Ain Range: 1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9289
AC SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless
otherwise noted.
Table 2.
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
SIGNAL-TO-NOISE RATIO (SINAD)
EFFECTIVE NUMBER OF BITS (ENOB)
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
WORST HARMONIC (Second or Third)
WORST OTHER (Excluding Second or Third)
TWO TONE INTERMOD DISTORTION (IMD)
DIGITAL SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless
otherwise noted.
Table 3.
Parameter
CLOCK INPUTS
LOGIC INPUTS (DFS, PDWN, SHARED_REF)
LOGIC OUTPUTS (LOCK)
DIGITAL OUTPUTS (D1+, D1–)
1
Clock inputs are LVDS-compatible. They require external dc bias and cannot be ac-coupled.
AIN1 and AIN2 = –7.0 dBFS
Logic Compliance
Differential Input Voltage
High Level Input Current
Low Level Input Current
Input Common-Mode Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Logic Compliance
Differential Output Voltage
Output Offset Voltage
Output Coding
1
(CLK+, CLK–)
Temperature
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
Full
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN1
IN2
= 2.4 MHz
= 10.3 MHz
= 35 MHz
= 2.4 MHz
= 10.3 MHz
= 35 MHz
= 2.4 MHz
= 10.3 MHz
= 35 MHz
= 2.4 MHz
= 10.3 MHz
= 35 MHz
= 2.4 MHz
= 10.3 MHz
= 35 MHz
= 2.4 MHz
= 10.3 MHz
= 35 MHz
= 15 MHz
= 16 MHz
Rev. 0 | Page 4 of 32
Test Level
IV
VI
VI
IV
V
V
IV
IV
V
V
IV
IV
VI
VI
VI
Temperature
Full
25°C
Full
Full
25°C
Full
Full
25°C
Full
Full
25°C
Full
Full
25°C
Full
Full
25°C
Full
25°C
Min
LVDS
250
1.125
2.0
2.45
LVDS
260
1.15
Twos complement or binary
Test Level
IV
V
VI
IV
V
VI
IV
V
VI
IV
V
VI
IV
V
VI
IV
V
VI
V
Typ
1.25
1.25
350
100
350
30
30
30
2
4
Min
47.7
46.7
47.6
46.2
7.6
7.4
61.0
54.0
Typ
49.0
48.5
48.0
48.9
48.4
47.5
7.8
7.7
7.6
70.0
68.0
65.0
–75.0
–70.0
–65.0
–70.0
–68.0
–65.0
–72.0
Max
450
75
75
1.375
0.8
0.05
440
1.35
Max
–61.0
–54.0
–61.0
–57.5
Unit
mV p-p
µA
µA
V
kΩ
pF
V
V
kΩ
pF
V
V
mV
V
Unit
dB
dB
dB
dB
dB
dB
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc