AD9289 Analog Devices, AD9289 Datasheet - Page 7

• Manufacturer Part Number: AD9289
• Description: Quad 8-Bit, 65 MSPS, Serial LVDS A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9289

• Resolution (bits): 8bit
• # Chan: 4
• Sample Rate: 65MSPS
• Interface: Ser
• Analog Input Type: Diff-Uni
• Ain Range: 1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin
No.
A1
B1
C1
D1
E1
F1
G1
H1
A2
B2
C2
D2
E2
F2
G2
H2
A3
B3
C3
D3
E3
F3
G3
H3
A4
B4
C4
D4
E4
F4
G4
H4
A5
B5
C5
Mnemonic
D1–A
D1+A
FCO+
DNC
AGND
VIN–A
VIN+A
LVDSBIAS
DNC
DNC
FCO–
DNC
AGND
AVDD
AGND
VIN+B
D1–B
D1+B
DRVDD
DRGND
AGND
CML
SHARED_REF
VIN–B
DNC
DNC
DCO+
LOCK
AVDD
REFT_A
REFB_A
SENSE
D1–C
D1+C
DCO–
1
3
Description
ADC A Complement Digital Output
ADC A True Digital Output
Frame Clock Output (MSB Indicator)
True Output
Do Not Connect
Analog Ground
ADC A Analog Input—Complement
ADC A Analog Input—True
LVDS Output Bias Pin
Do Not Connect
Do Not Connect
Frame Clock Output (MSB Indicator)
Complement Output
Do Not Connect
Analog Ground
Analog Supply
Analog Ground
ADC B Analog Input—True
ADC B Complement Digital Output
ADC B True Digital Output
Digital Supply
Digital Ground
Analog Ground
Common Mode Level Output ( = AVDD/2)
Shared Reference Control Bit
ADC B Analog Input—Complement
Do Not Connect
Do Not Connect
Data Clock Output—True
PLL Lock Output
Analog Supply
Reference Buffer Decoupling (Positive)
Reference Buffer Decoupling (Negative)
Reference Mode Selection
ADC C Complement Digital Output
ADC C True Digital Output
Data Clock Output—Complement
Figure 3. BGA Top View (Looking Through)
A
B
C
D
G
H
E
F
1 2 3 4 5 6 7 8
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Pin
No.
D5
E5
F5
G5
H5
A6
B6
C6
D6
E6
F6
G6
H6
A7
B7
C7
D7
E7
F7
G7
H7
A8
B8
C8
D8
E8
F8
G8
H8
1
2
3
4
LVDSBIAS use a 3.9 kΩ resistor-to-analog ground to set the LVDS output
differential swing of 350 mV p-p.
DFS has an internal on-chip pull-down resistor and defaults to offset binary
output coding if untied. If twos complement output coding is desired then
tie this pin to AVDD.
To enable, tie this pin to AVDD. To disable, tie this pin to AGND.
DTP has an internal on-chip pull-down resistor.
Mnemonic
AGND
AGND
REFT_B
REFB_B
VREF
DNC
DNC
DRVDD
DRGND
AVDD
AGND
AGND
VIN–C
D1–D
D1+D
DFS
AGND
AGND
AVDD
AGND
VIN+C
DNC
DNC
CLK+
CLK–
PDWN
VIN–D
VIN+D
DTP
2
3
, 4
3
Reference Buffer Decoupling (Positive)
Reference Buffer Decoupling (Negative)
Description
Analog Ground
Analog Ground
Voltage Reference Input/Output
Do Not Connect
Do Not Connect
Digital Supply
Digital Ground
Analog Supply
Analog Ground
Analog Ground
ADC C Analog Input—Complement
ADC D Complement Digital Output
ADC D True Digital Output
Data Format Select
Analog Ground
Analog Ground
Analog Supply
Analog Ground
ADC C Analog Input—True
Do Not Connect
Do Not Connect
Input Clock—True
Input Clock—Complement
Power Down Selection
ADC D Analog Input—Complement
ADC D Analog Input—True
Digital Test Pattern
AD9289