ADP5041 Analog Devices, ADP5041 Datasheet - Page 35

• Manufacturer Part Number: ADP5041
• Description: Micro PMU with 1.2 A Buck, Two 300 mA LDOs, Supervisory, Watchdog and Manual Reset
• Manufacturer: Analog Devices

Data Sheet
The inductor losses are estimated (without core losses) by
where:
DCR
I
where r is the normalized inductor ripple current.
where:
L is inductance.
f
D is duty cycle.
The
the power switch conductive losses, the switch losses, and the
transition losses of each channel. There are other sources of
loss, but these are generally less significant at high output load
currents, where the thermal limit of the application is. Equation 8
shows the calculation made to estimate the power dissipation in
the buck regulator.
The power switch conductive losses are due to the output current,
I
switches that have internal resistance, R
amount of conductive power loss is found by:
For the
3.6 V, R
0.16 Ω. At VIN1 = 2.3 V, these values change to 0.31 Ω and
0.21 Ω respectively, and at VIN1 = 5.5 V, the values are 0.16 Ω
and 0.14 Ω, respectively.
Switching losses are associated with the current drawn by the
driver to turn on and turn off the power devices at the switching
frequency. The amount of switching power loss is given by:
where:
C
C
For the
150 pF.
The transition losses occur because the PMOSFET cannot be
turned on or off instantaneously, and the SW node takes some
time to slew from near ground to near V
ground). The amount of transition loss is calculated by:
SW
OUT1(RMS)
OUT1
GATE-P
GATE-N
is switching frequency.
ADP5041
, flowing through the PMOSFET and the NMOSFET power
r ≈ V
D = V
P
P
P
P
L
P
I
OUT1
DBUCK
COND
SW
TRAN
is the inductor series resistance.
L
is the PMOSFET gate capacitance.
DSON-P
is the NMOSFET gate capacitance.
ADP5041
ADP5041
≅
is the rms load current of the buck regulator.
= (C
OUT1
(
I
= V
RMS
= [R
OUT1
OUT1
= P
is approximately 0.2 Ω, and R
GATE-P
)
× (1-D)/(I
IN1
buck regulator power dissipation, P
/V
(
COND
DSON-P
=
RMS
IN1
× I
, at 125°C junction temperature and VIN1 =
, the total of (C
I
OUT1
)
+ C
2
+ P
OUT1
× D + R
×
GATE-N
×
DCR
SW
× (t
OUT1
+ P
1
+
L
) × V
RISE
× L × f
DSON-N
TRAN
r
/12
+ t
GATE-P
IN1
FALL
× (1 − D)] × I
2
SW
× f
)
) × f
+ C
SW
DSON-P
OUT1
DSON-N
GATE-N
SW
(and from V
and R
) is approximately
is approximately
OUT1
DBUCK
DSON-N
2
, includes
. The
OUT1
(10)
(11)
Rev. 0 | Page 35 of 40
(4)
(5)
(6)
(7)
(8)
(9)
to
where t
switching node, SW. For the
SW are in the order of 5 ns.
If the preceding equations and parameters are used for
estimating the converter efficiency, it must be noted that the
equations do not describe all of the converter losses, and the
parameter values given are typical numbers. The converter
performance also depends on the choice of passive components
and board layout; therefore, a sufficient safety margin should be
included in the estimate.
LDO Regulator Power Dissipation
The power loss of a LDO regulator is given by:
where:
I
V
respectively.
I
Power dissipation due to the ground current is small and it
can be ignored.
The total power dissipation in the
Junction Temperature
In cases where the board temperature, T
thermal resistance parameter, θ
junction temperature rise. T
the formula
The typical θ
38°C/W (see Table 7). A very important factor to consider is
that θ
per JEDEC standard, and real applications may use different
sizes and layers. To remove heat from the device, it is important
to maximize the use of copper. Copper exposed to air dissipates
heat better than copper used in the inner layers. The exposed
pad (EP) should be connected to the ground plane with several
vias as shown in Figure 114.
If the case temperature can be measured, the junction temperature
is calculated by
where:
T
θ
Table 7.
When designing an application for a particular ambient
temperature range, calculate the expected
dissipation (P
Equation 8 to Equation 13. From this power calculation, the
junction temperature, T
LOAD
GND
JC
C
IN
is the case temperature.
is the junction-to-case thermal resistance provided in
and V
is the ground current of the LDO regulator.
P
P
T
T
is the load current of the LDO regulator.
JA
DLDO
D
J
J
= T
= T
RISE
= {[P
is based on a 4-layer, 4 inch × 3 inch, 2.5 oz copper, as
OUT
= [(V
and t
A
C
+ (P
+ (P
DBUCK
JA
are input and output voltages of the LDO,
D
) due to the losses of all channels by using
value for the 20-lead, 4 mm × 4 mm LFCSP is
FALL
IN
D
D
− V
+ P
× θ
× θ
are the rise time and the fall time of the
JC
JA
DLDO1
OUT
)
)
J
, can be estimated using Equation 14.
) × I
+ P
J
ADP5041
LOAD
is calculated from T
DLDO2
JA
] + (V
, can be used to estimate the
ADP5041
]}
, the rise and fall times of
IN
A
× I
, is known, the
ADP5041
GND
simplifies to:
)
A
ADP5041
and P
power
D
using
(12)
(13)
(14)
(15)