TDA8596 NXP Semiconductors, TDA8596 Datasheet - Page 30

The TDA8596 is a quad Bridge Tied Load (BTL) audio power amplifier with symmetricalinputs, made in BCDMOS technology

TDA8596

Manufacturer Part Number
TDA8596
Description
The TDA8596 is a quad Bridge Tied Load (BTL) audio power amplifier with symmetricalinputs, made in BCDMOS technology
Manufacturer
NXP Semiconductors
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TDA8596TH
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
TDA8596TH/N1S
Manufacturer:
NXP/恩智浦
Quantity:
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NXP Semiconductors
Table 17.
Refer to test circuit (see
Tested at T
TDA8596_2
Product data sheet
Symbol
t
t
t
t
t
d(mute_off)
amp_on
off
d(mute-on)
d(soft_mute)
amb
Characteristics
= 25 C; guaranteed for T
Parameter
mute off delay time
amplifier on time
amplifier switch-off
time
mute to on delay time from 10 % to 90 % of output signal;
soft mute delay time
Figure
…continued
29) at V
P
amb
Conditions
mute to 10 % of output signal;
I
amplifier from mute to 90 % of output
signal; I
time to DC output voltage < 0.1 V;
I
IB2[D1] = 1 to 0; V
Figure 6
from 10 % to 90 % of output signal;
IB2[D1] = 0 to 1; V
Figure 6
= 14.4 V; R
LO(SVR)
2
C-bus mode (IB1[D0]); I
I
I
DC load (IB1[D1] = 0); low pop
disabled (IB2[D3] = 1); see
I
I
active (IB1[D1] = 1); low pop disabled
(IB2[D3] = 1); see
I
I
active (IB1[D1] = 0); low pop enabled
(IB2[D3] = 0); see
legacy mode; with I
+20 ms; V
see
I
I
DC load (IB1[D1] = 0); low pop
disabled (IB2[D3] = 1); see
I
I
active (IB1[D1] = 1); low pop disabled
(IB2[D3] = 1); see
I
I
active (IB1[D1] = 0); low pop enabled
(IB2[D3] = 0); see
legacy mode; with I
+20 ms; V
see
with I
pop enabled (IB2[D3] = 0); see
Figure 4
with I
pop disabled (IB2[D3] = 1); see
Figure 5
I
2
LO(SVR)
2
LO(SVR)
2
LO(SVR)
2
LO(SVR)
2
LO(SVR)
2
LO(SVR)
2
= 40 C to +105 C.
C-bus mode (IB1[D0]); with
C-bus mode (IB1[D0]); with
C-bus mode (IB1[D0]); with
C-bus mode (IB1[D0]); with
C-bus mode (IB1[D0]); with
C-bus mode (IB1[D0]); with
C-bus controlled 4
Figure 6
Figure 6
LO(SVR)
LO(SVR)
LO(SVR)
= 0 A
Rev. 02 — 8 November 2007
= 10 A
= 10 A
= 10 A
= 10 A
= 10 A
= 10 A
L
STB
STB
= 4 ; f = 1 kHz; R
= 10 A
= 10 A
= 0 A
= 7 V; R
= 7 V; R
i
i
= 50 mV; see
= 50 mV; see
Figure 4
Figure 5
Figure 4
Figure 5
LO(SVR)
LO(SVR)
+15 ms; no
+20 ms; DC load
+20 ms; DC load
+30 ms; no
+35 ms; DC load
+30 ms; DC load
ADSEL
ADSEL
LO(SVR)
+0 ms; low
+0 ms; low
= 10 A
= 10 A
45 W power amplifier with symmetrical inputs
Figure 3
Figure 3
= 0 ;
= 0 ;
S
= 0 A
= 0 ; normal mode; unless otherwise specified.
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
Min
295
500
640
430
360
565
710
510
120
140
-
-
Typ
465
640
830
650
520
695
890
720
245
280
20
20
TDA8596
© NXP B.V. 2007. All rights reserved.
Max
795
940
1190
1030
870
1015
1270
1120
530
620
40
40
30 of 48
Unit
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms

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