TDF8599A NXP Semiconductors, TDF8599A Datasheet
TDF8599A
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TDF8599A Summary of contents
Page 1
... W/2 Rev. 02 — 30 June 2009 1. General description The TDF8599A is a dual Bridge-Tied Load (BTL) car audio amplifier comprising an NDMOST-NDMOST output stage based on SOI BCDMOS technology. Low power dissipation enables the TDF8599A high-efficiency, class-D amplifi used with a smaller heat sink than those normally used with standard class-AB amplifiers. ...
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... V; THD = THD = THD = describes and measurement. DSon Description plastic, heatsink small outline package; 36 leads; low stand-off height Rev. 02 — 30 June 2009 TDF8599A Min Typ [ ...
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... SSM 12 MOD STABI DDD MODE 16 SELECT SCL + 15 2 SDA I C-BUS 11 ADS 36 GNDD/HW Block diagram Rev. 02 — 30 June 2009 TDF8599A STABI1 V P1 DRIVER HIGH PWM DRIVER LOW PGND1 V P1 DRIVER HIGH PWM DRIVER LOW PGND1 V P2 ...
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... BOOT2P 26 25 PGND2 BOOT2N 23 OUT2N 22 21 VSTAB2 DCP 20 OSCIO 19 Heatsink up (top view) pin configuration TDF8599ATH Pin description [1] Pin Type Description 1 I channel 1 positive audio input 2 I channel 1 negative audio input 3 I channel 2 positive audio input 4 I channel 2 negative audio input ...
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... Functional description 8.1 General The TDF8599A is a dual full bridge (BTL) audio power amplifier using class-D technology. The audio input signal is converted into a Pulse-Width Modulated (PWM) signal using the analog input and PWM control stages. A PWM signal is applied to driver circuits for both high-side and low-side enabling the DMOS power output transistors to be driven ...
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... The TDF8599A is enabled when pin EN is HIGH. When pin EN is LOW, the TDF8599A is off and the supply current is at its lowest value (typically 2 A). When off, the TDF8599A is completely deactivated and will not react to I ...
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... Pin SEL_MUTE HIGH (S1 open) LOW (S1 closed) [ has no influence on the oscillator frequency. It does osc Figure 5 connected between pins OSCSET and AGND, the TDF8599A is in Master Mode setting pin OSCIO Settings Pin OSCSET R > osc shorted to pin AGND osc Rev. 02 — ...
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... In Slave mode, an internal watchdog timer on pin OSCIO is triggered when the TDF8599A is switched off by pulling down pin EN. If the external clock fails, the watchdog timer forces the TDF8599A to switch off ...
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... SSM osc C osc 001aai773 f osc C-bus mode, this frequency can be varied by osc ). Rev. 02 — 30 June 2009 TDF8599A Equation and is calculated as 100 A 100 A OSCSET R osc SSM SSM C SSM 001aai774 b. On and 1. see Figure 7. osc 2: (2) ...
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... OSCIO pin SSM pin output C to pin AGND SSM output shorted to pin AGND input PLL input shorted to pin AGND Rev. 02 — 30 June 2009 TDF8599A Section 8.4.2 on page 13. Phase lock operation Figure , C and R depend on the desired PLL_s PLL_p PLL is given by 8.4 B PLL PLL ...
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... See C-bus mode, pin MOD is latched using the I amplifier switching interference generating incorrect information on pin MOD. In non-I one of the TDF8599A’s outputs starts switching. 8.4.1 Modulation mode In non-I Table 8 • AD modulation mode: the bridge halves switch in opposite phase. • ...
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... Product data sheet 2 I C-bus controlled dual channel class-D power amplifi INxP OUTP AD BD AD/BD modulation switching circuit INxP OUTxP INxN OUTxN Rev. 02 — 30 June 2009 TDF8599A +V P OUTN INxN 001aai778 001aai779 001aai780 © NXP B.V. 2009. All rights reserved ...
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... MOD Table 8 for selection of the phase shift in non-I Figure 8). An example of using Rev. 02 — 30 June 2009 TDF8599A 001aai781 001aai782 can be selected using the C-bus mode with pin ...
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... The inputs and outputs for Parallel mode must be connected on the Printed-Circuit Board (PCB) as shown in as shown in Fig 13. Parallel mode In Parallel mode, the channel 1 I 8.5 Protection The TDF8599A includes a range of built-in protection functions. How the TDF8599A manages the various possible fault conditions for each protection is described in the following sections: TDF8599A_2 Product data sheet 2 I C-bus controlled dual channel class-D power amplifi ...
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... TDF8599A_2 Product data sheet 2 I C-bus controlled dual channel class-D power amplifier Overview of protection types th(j-a) ) > 160 C, OverTemperature Protection (OTP Rev. 02 — 30 June 2009 TDF8599A Reference Section 8.5.1 Section 8.5.2 Section 8.5.3 Section 8.5.4 Section 8.5.5 Section 8.5.6 Section 8.5.6 create a junction temperature around the © NXP B.V. 2009. All rights reserved. ...
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... DB1[D2] is set and if bit IB1[D7] is not set, diagnostic information is also given. Any detected offset shuts down both channels when bit IB2[D7] is not set. To restart the TDF8599A must be toggled or DCP disabled by connecting pin DCP to pin AGND. ...
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... C-bus controlled dual channel class-D power amplifier 2 C-bus mode, when an offset is detected, DCP always gives diagnostic Overview of TDF8599A protection circuits and amplifier states C-bus mode deep supply voltage drops will cause a Power-On Reset (POR). The restart requires an 2 C-bus mode and non-I Rev. 02 — ...
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... AMPLIFIER RESTART pull up V AGND = C-bus mode only) 2 C-bus mode and is controlled using bit IB2[D2]. det(DCload) Rev. 02 — 30 June 2009 TDF8599A 2 2 C-bus. The I C-bus bits are set 2 C-bus read command. 2 C-bus read command is 2 C-bus latches ...
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... DRIVER LOW PGND2 out (V) out out+ t d(stb-mute) Figure 3 on page Figure 18. SPEAKER LOAD 0 25 350 Rev. 02 — 30 June 2009 TDF8599A V P OUTN OUTP 001aai787 t (s) t det(DCload) 001aai788 6) is used to create an OPEN LOAD 001aaj956 © NXP B.V. 2009. All rights reserved. ...
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... OCP bits DB1[D3] and DB2[D3 Section 8.6.2.2 “Recommended start-up sequence with DC load for detailed information. (Figure 19) illustrates the TDF8599A’s ability to perform a DC load Rev. 02 — 30 June 2009 TDF8599A Description speaker load shorted load open load © NXP B.V. 2009. All rights reserved. ...
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... DB1[D6 load valid YES 2 I C-bus TX startup disable DC load enable channel 1 enable channel 2 2 C-bus mode and is controlled using bit IB3[D4]. Rev. 02 — 30 June 2009 TDF8599A 2 I C-bus TX startup enable DC load disable channel 1 disable channel 2 restart DC load NO YES COUNTMAX ERROR HANDLING ...
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... In Master mode, the clock is kept active by an additional delay (t approximately allow slave devices to enter the off state. When an external clock is connected to pin OSCIO (in Slave mode), the clock must remain active during the shutdown sequence for delay (t TDF8599A devices are able to enter the off state. V DDA DIAG ...
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... Short circuited to ground C-bus mode, pins MOD and ADS can be latched using the I IB3[D7 This avoids disturbances from amplifier outputs of other TDF8599A devices in the same application switching and generating incorrect information on the MOD and ADS pins. TDF8599A_2 Product data sheet ...
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... NXP Semiconductors 2 In non-I latched when one of the TDF8599A’s outputs starts switching. SCL SDA M p START (1) SLAVE (1) When SCL is HIGH, SDA changes to form the start or stop condition. 2 Fig 22. I C-bus start and stop conditions SCL 1 2 SDA MSB MSB ...
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... NXP Semiconductors 9.1 Instruction bytes If R/W bit = 0, the TDF8599A expects three instruction bytes: IB1, IB2 and IB3. After a power-on reset, all unspecified instruction bits must be set to zero. Table 14. Instruction byte descriptions Bit Value Description Instruction byte IB1 D7 0 offset detection on pin DIAG ...
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... NXP Semiconductors 9.2 Data bytes If R the TDF8599A sends two data bytes to the microprocessor (DB1 and DB2). All short diagnostic and offset protection bits are latched. In addition, all bits are reset after a read operation except the DC load detection bits (DBx[D4], DB1[D6]). The default setting for all bits is logic 0 ...
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... Current limiting concept. [3] Human Body Model (HBM). [4] Charged-Device Model (CDM). [5] The output pins are defined as the output pins of the filter connected between the TDF8599A output pins and the load. TDF8599A_2 Product data sheet 2 I C-bus controlled dual channel class-D power amplifier ...
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... EN; Mute mode or Operating 2 mode; non-I C-bus mode pin SEL_MUTE; Mute mode; voltage on pin EN > pin SEL_MUTE; Operating mode; voltage on pin EN > pin EN; 2.5 V pin SEL_MUTE; Operating mode; 0.8 V Rev. 02 — 30 June 2009 TDF8599A Conditions Typ 35 1 Min Typ 8 14 ...
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... Mute mode and Operating mode undervoltage; amplifier is muted overvoltage; load dump protection is activated V that a POR occurs at P current limiting concept gain = 1 dB IB2[D3 non-I IB2[D3 [7] for normal speaker load; DB1[D4 DB2[D4 DB1[D4 DB2[D4 Rev. 02 — 30 June 2009 TDF8599A Min Typ - 0.2 [2][ 2.45 2 2.45 6.9 7 ...
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... V stereo mode parallel mode at supply voltage equal to or below 35 V stereo mode parallel mode Section 9 on page th(offset) Section 8.6.2.1 on page 18. The DC load enable bit IB2[D2] must be reset after each load Rev. 02 — 30 June 2009 TDF8599A Min 2 [5] C-bus - [ [6] - ...
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... Spread spectrum mode activated SSM change positive; IB1[D4 IB1[D3 change negative; IB1[D4 IB1[D3 PWM output PWM output Rev. 02 — 30 June 2009 TDF8599A Min Typ Max Unit - 320 - kHz 300 - 450 kHz ...
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... LC filter in the application together with all resistance from PCB s(L) traces or wiring between the output pin of the TDF8599A and the inductor to the measurement point. LC filter dimensioning for 4 load and 2.2 F for 2 ...
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... Hz (typically 320 kHz o(2) and Figure 27 show the estimated output power at THD = 0.5 % and Rev. 02 — 30 June 2009 Equation 2 f osc --------- - V w min 1. TDF8599A 5: (5) where o 1 © NXP B.V. 2009. All rights reserved ...
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... C-bus controlled dual channel class-D power amplifier 001aaj181 ( ( 0. (minimum). in stereo mode with Fig 27. P and Figure 29 show the estimated output power at THD = 0.5 % and Rev. 02 — 30 June 2009 TDF8599A 160 P o 120 ( THD = 0.2 (at T ...
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... P = 0.025 , (minimum). in parallel mode with Fig 29 [ DSon s = on-resistance of power switch ( ) speaker can be used with a supply voltage before current limiting Rev. 02 — 30 June 2009 TDF8599A 300 o 250 200 (1) 150 (2) 100 ( THD = 0.1 ...
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... Remark: When using a 1 after the low-pass filter switches two 2 14.5 Heat sink requirements In most applications necessary to connect an external heat sink to the TDF8599A. Thermal foldback activates at T between the maximum power dissipation before activation of thermal foldback and the total thermal resistance from junction to ambient: ...
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... 001aaj185 THD + N (%) (W) o (1) V (2) V (3) V Fig 31. THD + function of output power with a Rev. 02 — 30 June 2009 TDF8599A (audio with crest factor of 10 (3) 1 ( 100 Hz. ...
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... Fig 33. THD + function of output power with a 001aaj190 THD + N (%) (Hz) (1) V (2) V Fig 35. THD + function of frequency with 14 Rev. 02 — 30 June 2009 TDF8599A (3) 1 ( 100 Hz. ...
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... Fig 37. Gain as a function of frequency = 001aaj193 (W) (3) (2) ( (V) P Fig 39. Output power as a function of supply voltage Rev. 02 — 30 June 2009 TDF8599A 240 P o 200 160 120 ...
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... C-bus controlled dual channel class-D power amplifier 001aaj195 (2) (dB) ( (Hz) Fig 41. Channel separation as a function of frequency 001aaj197 (%) (W) o Fig 43. Efficiency as a function of total output power Rev. 02 — 30 June 2009 TDF8599A (2) 90 (1) 100 14 (1) Channel 1 to channel 2 ...
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... P (W) o Fig 45. Efficiency as a function of total output power 70 CMRR (dB Rev. 02 — 30 June 2009 TDF8599A 100 with both channels driven 001aak079 (Hz) 001aaj200 ...
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... OUT1N IN2N 470 ACGND BOOT1N ACGND 32 5 100 SEL_MUTE PGND1 30 7 BOOT1P SVRR 29 8 OUT1P AGND 28 9 TDF8599A 2 OUT2P DDA 27 10 bead BOOT2P ADS 26 11 4.7 k PGND2 MOD CLIP BOOT2N DIAG 23 14 ...
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... C ACGND BOOT1N ACGND 32 5 100 100 nF (1) SEL_MUTE PGND1 30 7 BOOT1P SVRR 29 8 OUT1P AGND 28 9 TDF8599A 2 OUT2P DDA 27 10 bead R ADS BOOT2P ADS PGND2 MOD 25 12 100 CLIP BOOT2N ...
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... C ACGND BOOT1N ACGND 32 5 100 100 nF (1) SEL_MUTE PGND1 30 7 BOOT1P SVRR 29 8 OUT1P AGND 28 9 TDF8599A 2 OUT2P DDA 27 10 bead R ADS BOOT2P ADS PGND2 MOD 25 12 100 CLIP BOOT2N ...
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... 100 nF (1) SEL_MUTE PGND1 30 7 PGND1 470 nF BOOT1P SVRR OUT1P AGND 28 9 TDF8599A 2 OUT2P DDA SLAVE PA bead R 2 ADS I C-bus BOOT2P ADS 26 11 address select 33 k PGND2 MOD parallel mode 25 12 setting ...
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... 0.32 16.0 13.0 1.1 11.1 6.2 2.9 0.23 15.8 12.6 0.9 10.9 5.8 2.5 REFERENCES JEDEC JEITA Rev. 02 — 30 June 2009 detail 14.5 1.1 1.7 0.65 0.25 0.12 13.9 0.8 1.5 EUROPEAN PROJECTION TDF8599A SOT851 2.55 8 0.03 0.07 2.20 0 ISSUE DATE 04-05-04 © NXP B.V. 2009. All rights reserved ...
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... Inspection and repair • Lead-free soldering versus SnPb soldering 17.3 Wave soldering Key characteristics in wave soldering are: TDF8599A_2 Product data sheet 2 I C-bus controlled dual channel class-D power amplifier Rev. 02 — 30 June 2009 TDF8599A © NXP B.V. 2009. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 52. Rev. 02 — 30 June 2009 TDF8599A Figure 52) than a SnPb process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © NXP B.V. 2009. All rights reserved. ...
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... Master microprocessor Most Significant Bit N-type double Diffused Metal-Oxide Semiconductor Transistor OverCurrent Protection OverTemperature Protection OverVoltage Protection Phase-Locked Loop Power-On Reset Pulse-Width Modulation Silicon On Insulator Rev. 02 — 30 June 2009 TDF8599A peak temperature time 001aac844 © NXP B.V. 2009. All rights reserved ...
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... Figure 20 on page Section 8.6.3: Figure 21 on page Section 14.7: Figure 47 on page Figure 50 on page 45. Objective data sheet Rev. 02 — 30 June 2009 TDF8599A Change notice Supersedes - TDF8599A_1 22. 23. 42, Figure 48 on page 43, Figure 49 on page © NXP B.V. 2009. All rights reserved ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 30 June 2009 TDF8599A © NXP B.V. 2009. All rights reserved ...
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... Table 12. Interpretation of DC load detection bits . . . . . .20 2 Table 13. I C-bus write address selection using 23. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Fig 2. Heatsink up (top view) pin configuration TDF8599ATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 3. Mode selection Fig 4. Clock frequency as a function of R Fig 5. Master and slave configuration . . . . . . . . . . . . . . .8 Fig 6. Spread spectrum mode . . . . . . . . . . . . . . . . . . . . .9 Fig 7 ...
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... C-bus mode . . . . . . . . . . . .45 Fig 51. Package outline SOT851-2 (HSOP36 .46 Fig 52. Temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 TDF8599A_2 Product data sheet 2 I C-bus controlled dual channel class-D power amplifier Rev. 02 — 30 June 2009 TDF8599A continued >> © NXP B.V. 2009. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com TDF8599A All rights reserved. Date of release: 30 June 2009 Document identifier: TDF8599A_2 ...