LPC1111FDH20 NXP Semiconductors, LPC1111FDH20 Datasheet - Page 7

The LPC1111FDH20 is an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/

LPC1111FDH20

Manufacturer Part Number
LPC1111FDH20
Description
The LPC1111FDH20 is an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/
Manufacturer
NXP Semiconductors
Datasheet

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Part Number:
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NXP Semiconductors
5. Block diagram
LPC111X
Product data sheet
Fig 1.
CT32B0_MAT[3:0]
CT32B1_MAT[3:0]
CT16B0_MAT[2:0]
CT16B1_MAT[1:0]
DTR, DSR, CTS
CT32B0_CAP0
CT32B1_CAP0
CT16B0_CAP0
CT16B1_CAP0
DCD, RI, RTS
(1) LQFP48 packages only.
(2) Not on LPC1112FDH20/102.
(3) All pins available on LQFP48 and HVQFN33 packages. CT16B1_MAT1 not available on TSSOP28/DIP28 packages.
(4) AD[7:0] available on LQFP48 and HVQFN33 packages. AD[5:0] available on TSSOP28/DIP28 packages. AD[4:0] available on
(5) All pins available on LQFP48 packages. RXD, TXD, DTR, CTS, RTS available on HVQFN 33 packages. RXD, TXD, CTS, RTS
GPIO ports
PIO0/1/2/3
CT32B1_MAT3, CT16B1_CAP0, CT16B1_MAT[1:0], CT32B0_CAP0 not available on TSSOP20/SO20 packages.
TSSOP20/SO20 packages.
available on TSSOP28/DIP28 packages. RXD, TXD available on TSSOP20/SO20 packages.
LPC1100/LPC1100L series block diagram
RXD
TXD
(5)
(5)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
,
LPC1110/11/12/13/14
HIGH-SPEED
GPIO
32-bit COUNTER/TIMER 0
32-bit COUNTER/TIMER 1
16-bit COUNTER/TIMER 0
16-bit COUNTER/TIMER 1
system bus
UART
slave
CORTEX-M0
TEST/DEBUG
INTERFACE
All information provided in this document is subject to legal disclaimers.
SWD
ARM
Rev. 7 — 1 March 2012
4/8/16/24/32 kB
slave
FLASH
AHB-LITE BUS
slave
AHB TO APB
BRIDGE
LPC1110/11/12/13/14/15
slave
1/2/4/8 kB
SRAM
POR
IRC
32-bit ARM Cortex-M0 microcontroller
slave
XTALOUT
SYSTEM CONTROL
POWER CONTROL,
ROM
GENERATION,
10-bit ADC
I
IOCONFIG
2
FUNCTIONS
C-BUS
SPI1
SYSTEM
SPI0
WDT
PMU
XTALIN
CLOCK
clocks and
controls
(1)
(2)
RESET
002aae696
© NXP B.V. 2012. All rights reserved.
CLKOUT
AD[7:0]
SCL
SDA
SCK0, SSEL0
MISO0, MOSI0
SCK1, SSEL1
MISO1, MOSI1
(4)
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