LPC1778FET180 NXP Semiconductors, LPC1778FET180 Datasheet - Page 88

• Manufacturer Part Number: LPC1778FET180
• Description: The LPC1778 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC178X_7X
Objective data sheet
Table 24.
T
[1]
[2]
[3]
[4]
Symbol
T
T
t
t
t
t
DS
DH
v(Q)
h(Q)
amb
Fig 21. SSP master timing in SPI mode
cy(PCLK)
cy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
T
T
SSP SCR parameter (specified in the SSP0CR0 register), and the SSP CPSDVSR parameter (specified in
the SSP clock prescale register).
T
T
T
=
cy(clk)
cy(clk)
amb
cy(clk)
amb

40
= 40 C to 85 C; V
= 25 C; V
= (SSPCLKDIV  (1 + SCR)  CPSDVSR) / f
is a function of the main clock frequency f
= 12  T
MOSI
MISO
MOSI
MISO

Dynamic characteristics: SSP pins in SPI mode
C to 85
Parameter
PCLK cycle time
clock cycle time
data set-up time
data hold time
data output valid time in SPI mode
data output hold time in SPI mode
All information provided in this document is subject to legal disclaimers.
cy(PCLK)
DD

= 3.3 V.
C, V
Rev. 3 — 27 December 2011
.
DD(REG)(3V3)
DATA VALID
DATA VALID
DD(REG)(3V3)
t
v(Q)
DATA VALID
Conditions
in SPI mode
T
DATA VALID
in SPI mode
cy(clk)
= 3.0 V to 3.6 V. Values guaranteed by design.
= 3.0 V to 3.6 V.
t
v(Q)
t
DS
DATA VALID
DATA VALID
main
main
, the SSP peripheral clock divider (SSPCLKDIV), the
t
clk(H)
t
. 3The clock cycle time derived from the SPI bit rate
t
DH
DS
32-bit ARM Cortex-M3 microcontroller
[3]
[3][4]
[3][4]
[3][4]
[3][4]
DATA VALID
DATA VALID
Min
10
120
14.8
2
-
2.4
t
clk(L)
t
DH
t
h(Q)
Typ
-
10.5
1
4.0
0.2
LPC178x/7x
t
h(Q)
© NXP B.V. 2011. All rights reserved.
Max
-
-
-
6.3
-
CPHA = 1
CPHA = 0
002aae829
88 of 120
Unit
ns
ns
ns
ns
ns
ns