P87C554 NXP Semiconductors, P87C554 Datasheet - Page 11

• Manufacturer Part Number: P87C554
• Description: The P87C554 Single-Chip 8-Bit Microcontroller is manufactured inan advanced CMOS process and is a derivative of the 80C51microcontroller family
• Manufacturer: NXP Semiconductors

configured as level-sensitive. Holding the pin low restarts the oscillator
Philips Semiconductors
Table 2. External Pin Status During Idle and Power-Down Modes
With an external interrupt, INT0 and INT1 must be enabled and
but bringing the pin back high completes the exit. Once the interrupt
is serviced, the next instruction to be executed after RETI will be the
one following the instruction that put the device into Power Down.
POWER OFF FLAG
The Power Off Flag (POF) is set by on-chip circuitry when the V
level on the P87C554 rises from 0 to 5 V. The POF bit can be set or
cleared by software allowing a user to determine if the reset is the
result of a power-on or a warm start after powerdown. The V
must remain above 3 V for the POF to remain unaffected by the V
level.
Design Consideration
2002 Mar 25
When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to
two machine cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this
event, but access to the port pins is not inhibited. To eliminate
the possibility of an unexpected write when Idle is terminated by
reset, the instruction following the one that invokes Idle should not
be one that writes to a port pin or to external memory.
80C51 8-bit microcontroller – 12 clock operation
16K/512 OTP/RAM, 8 channel 10-bit A/D, I
capture/compare, high I/O
Idle
Idle
Power-down
Power-down
MODE
If logic 1s are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is (00X00000).
BIT
PCON.7
PCON.6
PCON.5
PCON.4
PCON.3
PCON.2
PCON.1
PCON.0
SYMBOL
SMOD1
SMOD0
POF
WLE
GF1
GF0
PD
IDL
PCON
(87H)
PROGRAM
MEMORY
External
External
Internal
Internal
FUNCTION
Double Baud rate bit. When set to logic 1, the baud rate is doubled when the serial port SIO0 is being
used in modes 1, 2, or 3.
Selects SM0/FE for SCON.7 bit.
Power Off Flag
Watchdog Load Enable. This flag must be set by software prior to loading timer T3 (watchdog timer). It is
cleared when timer T3 is loaded.
General-purpose flag bit.
General-purpose flag bit.
Power-down bit. Setting this bit activates the power-down mode. It can only be set if input EW is high.
Idle mode bit. Setting this bit activates the Idle mode.
SMOD1
(MSB)
7
ALE
SMOD0
1
1
0
0
6
Figure 3. Power Control Register (PCON)
PSEN
POF
5
1
1
0
0
CC
2
C, PWM,
CC
level
WLE
CC
4
PORT 0
Data
Float
Data
Float
9
ONCE
The ONCE (“On-Circuit Emulation”) Mode facilitates testing and
debugging of systems without the device having to be removed from
the circuit. The ONCE Mode is invoked by:
1. Pull ALE low while the device is in reset and PSEN is high;
2. Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins go into a float
state, and the other port pins and ALE and PSEN are weakly pulled
high. The oscillator circuit remains active. While the device is in this
mode, an emulator or test CPU can be used to drive the circuit.
Normal operation is restored when a normal reset is applied.
Reduced EMI Mode
The ALE-Off bit, AO (AUXR.0) can be set to disable the ALE output.
It will automatically become active when required for external
memory accesses and resume to the OFF state after completing the
external memory access.
GF1
3
PORT 1
Data
Data
Data
Data
GF0
Mode
2
Address
PORT 2
Data
Data
Data
PD
1
(LSB)
PORT 3
IDL
0
Data
Data
Data
Data
PORT 4
Data
Data
Data
Data
P87C554
SU00954
Product data
PWM0/
PWM1
High
High
High
High