P89LPC932A1 NXP Semiconductors, P89LPC932A1 Datasheet
P89LPC932A1
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P89LPC932A1 Summary of contents
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... The P89LPC932A1 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC932A1 in order to reduce component count, board space, and system cost. 2. Features 2 ...
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... I Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times. I Only power and ground connections are required to operate the P89LPC932A1 when internal reset option is selected. I Four interrupt priority levels. I Eight keypad interrupt inputs, plus two additional external interrupt inputs. ...
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... Enhancements added to the ISP/IAP code to improve code safety and increase ISP/IAP functionality. This may require slight changes to original P89LPC932 code using IAP function calls. Some ISP/IAP settings are different than the original P89LPC932. Tools designed to support the P89LPC932A1 should be used to program this device, such as Flash Magic version 1.98, or later. 3. Ordering information Table 1 ...
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... PORT 1 CONFIGURABLE I/Os PORT 0 CONFIGURABLE I/Os KEYPAD INTERRUPT WATCHDOG TIMER AND OSCILLATOR PROGRAMMABLE CPU OSCILLATOR DIVIDER clock ON-CHIP CONFIGURABLE RC OSCILLATOR OSCILLATOR Rev. 03 — 12 March 2007 P89LPC932A1 TXD UART RXD SCL 2 I C-BUS SDA SPICLK MISO SPI MOSI SS REAL-TIME CLOCK/ SYSTEM TIMER TIMER 0 T0 ...
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... NXP Semiconductors 5. Functional diagram CLKOUT Fig 2. Functional diagram of P89LPC932A1 6. Pinning information 6.1 Pinning Fig 3. P89LPC932A1 TSSOP28 pin configuration P89LPC932A1_3 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core KBI0 CMP2 KBI1 CIN2B KBI2 CIN2A KBI3 CIN1B PORT 0 KBI4 CIN1A KBI5 ...
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... NXP Semiconductors Fig 4. P89LPC932A1 PLCC28 pin configuration Fig 5. P89LPC932A1 HVQFN28 pin configuration P89LPC932A1_3 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core 5 P1.6/OCB P1.5/RST P89LPC932A1FA 8 P3.1/XTAL1 9 P3.0/XTAL2/CLKOUT P1.4/INT1 10 P1.3/INT0/SDA 11 terminal 1 index area 1 P1.6/OCB 2 P1.5/RST P89LPC932A1FHN 4 P3 ...
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... NXP Semiconductors Fig 6. P89LPC932A1 DIP28 pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin TSSOP28, HVQFN28 PLCC28, DIP28 P0.0 to P0.7 P0.0/CMP2 KBI0 P0.1/CIN2B KBI1 P0.2/CIN2A KBI2 P0.3/CIN1B KBI3 P89LPC932A1_3 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core 1 P2 ...
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... P1.3 — Port 1 bit 3 (open-drain when used as output). I INT0 — External interrupt 0 input. 2 I/O SDA — serial data input/output. I P1.4 — Port 1 bit 4. I INT1 — External interrupt 1 input. Rev. 03 — 12 March 2007 P89LPC932A1 Section 7.13.1 “Port for details. P1.2 and © NXP B.V. 2007. All rights reserved ...
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... SPICLK — SPI clock. When configured as master, this pin is output; when configured as slave, this pin is input. I/O P2.6 — Port 2 bit 6. O OCA — Output Compare A. Rev. 03 — 12 March 2007 P89LPC932A1 falls below the DD Section 7.13.1 “Port configurations” for details. © NXP B.V. 2007. All rights reserved ...
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... XTAL1/XTAL2 are not used to generate the clock for the RTC/system timer. I Ground reference. I Power supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes. Rev. 03 — 12 March 2007 P89LPC932A1 Section 7.13.1 “Port configurations” for details. © NXP B.V. 2007. All rights reserved ...
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... NXP Semiconductors 7. Functional description Remark: Please refer to the P89LPC932A1 User manual for a more detailed functional description. 7.1 Special function registers Remark: Special Function Registers (SFRs) accesses are restricted in the following ways: • User must not attempt to access any SFR locations not defined. ...
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Table 3. Special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* Accumulator E0H AUXR1 Auxiliary function register A2H Bit address B* B register F0H BRGR0 Baud rate generator rate low BEH BRGR1 ...
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Table 3. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR addr. 2 I2DAT I C data register DAH I2SCLH Serial clock generator/SCL DDH duty cycle register high I2SCLL Serial clock generator/SCL DCH duty cycle ...
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Table 3. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR addr. OCRBH Output compare B register FBH high OCRBL Output compare B register FAH low OCRCH Output compare C register FDH high OCRCL Output ...
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Table 3. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR addr. PCONA Power control register A B5H Bit address PSW* Program status word D0H PT0AD Port 0 digital input disable F6H RSTSRC Reset source ...
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... All ports are in input only (high-impedance) state after power-up. [3] The RSTSRC register reflects the cause of the P89LPC932A1 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx11 0000. [4] The only reset source that affects these SFRs is power-on reset. ...
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... NXP Semiconductors 7.2 Enhanced CPU The P89LPC932A1 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles. 7.3 Clocks 7.3.1 Clock definitions The P89LPC932A1 device has several internal clocks as defined below: OSCCLK — ...
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... Idle mode, it may be turned off prior to entering Idle, saving additional power. 7.4 On-chip RC oscillator option The P89LPC932A1 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory preprogrammed value to adjust the oscillator frequency to 7.373 MHz End-user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies ...
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... Low power select The P89LPC932A1 is designed to run at 12 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance access ...
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... CODE Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC932A1 has on-chip Code memory. The P89LPC932A1 also has 512 bytes of on-chip Data EEPROM that is accessed via SFRs (see 7.11 Data RAM arrangement The 768 bytes of on-chip RAM are organized as shown in Table 4 ...
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... Fig 8. Interrupt sources, interrupt enables, and power-down wake-up sources 7.13 I/O ports The P89LPC932A1 has four I/O ports: Port 0, Port 1, Port 2, and Port 3. Ports 0, 1 and 2 are 8-bit ports, and Port 2-bit port. The exact number of I/O pins available depends upon the clock and reset options chosen, as shown in Table 5 ...
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... Required for operation above 12 MHz. 7.13.1 Port configurations All but three I/O port pins on the P89LPC932A1 may be configured by software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port select the output type for each port pin. 1. P1.5 (RST) can only be an input and cannot be confi ...
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... Table 8 “Static characteristics” (see Table 8 “Static characteristics”), and is negated when the P89LPC932A1 device is to operate with a power supply that can be bo Rev. 03 — 12 March 2007 P89LPC932A1 for detailed specifications. falls below the brownout ...
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... Power-down mode The Power-down mode stops the oscillator in order to minimize power consumption. The P89LPC932A1 exits Power-down mode via any reset, or certain interrupts. In Power-down mode, the power supply voltage may be reduced to the data retention voltage V retains the RAM contents at the point where Power-down mode was entered. SFR contents are not guaranteed after V recommended to wake up the processor via reset in this case ...
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... The Boot address will be used if a UART break reset occurs, or the non-volatile Boot Status bit (BOOTSTAT. the device is forced into ISP mode during power-on (see P89LPC932A1 User manual ). Otherwise, instructions will be fetched from address 0000H. 7.17 Timers/counters 0 and 1 The P89LPC932A1 has two general purpose counter/timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1. Both can be confi ...
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... RTC/system timer The P89LPC932A1 has a simple RTC that allows a user to continue running an accurate timer while the rest of the device is powered-down. The RTC can be a wake- interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter. When it reaches all logic 0s, the counter will be reloaded again and the RTCF fl ...
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... An event counter can be set to delay a capture by a number of capture events. P89LPC932A1_3 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Rev. 03 — 12 March 2007 P89LPC932A1 © NXP B.V. 2007. All rights reserved ...
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... Fig 10. Symmetrical PWM P89LPC932A1_3 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core TOR2 compare value timer value 0x0000 non-inverted inverted TOR2 compare value timer value 0 non-inverted inverted Rev. 03 — 12 March 2007 P89LPC932A1 002aaa893 002aaa894 © NXP B.V. 2007. All rights reserved ...
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... Since N ranges from 0 to 15, the CCLK frequency can be in the range of PCLK to P89LPC932A1_3 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core PCLK = ----------------- - Rev. 03 — 12 March 2007 P89LPC932A1 TOR2 COMPARE VALUE A (or C) COMPARE VALUE B (or D) TIMER VALUE 0 PWM OUTPUT (OCA or OCC) PWM OUTPUT (OCB or OCD) 002aaa895 Equation 1. ...
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... The P89LPC932A1 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The P89LPC932A1 does include an independent Baud Rate Generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent Baud Rate Generator ...
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... Section 7.20.5 “Baud rate generator and 7.20.5 Baud rate generator and selection The P89LPC932A1 enhanced UART has an independent Baud Rate Generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1 but is much more accurate ...
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... If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data. P89LPC932A1_3 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core bit (bit 8) in double buffering (modes 1, 2 and 3) Rev. 03 — 12 March 2007 P89LPC932A1 © NXP B.V. 2007. All rights reserved ...
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... C-bus configuration is shown in 2 C-bus interface that supports data transfers up to 400 kHz C-bus P1.3/SDA P1.2/SCL P89LPC932A1 2 C-bus configuration Rev. 03 — 12 March 2007 P89LPC932A1 Figure 14. The P89LPC932A1 device provides OTHER DEVICE OTHER DEVICE 2 2 WITH I C-BUS WITH I C-BUS INTERFACE ...
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... STAGE INPUT FILTER OUTPUT STAGE timer 1 overflow P1.2 I2CON I2SCLH I2SCLL status bus I2STAT 2 C-bus serial interface block diagram Rev. 03 — 12 March 2007 P89LPC932A1 8 I2ADR ADDRESS REGISTER COMPARATOR SHIFT REGISTER ACK I2DAT 8 BIT COUNTER / ARBITRATION TIMING AND SYNC LOGIC AND CONTROL LOGIC ...
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... NXP Semiconductors 7.22 Serial Peripheral Interface (SPI) The P89LPC932A1 provides another high-speed serial communication interface—the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode Mbit/s can be supported in Master mode Mbit/s in Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection ...
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... SHIFT MOSI REGISTER SPICLK SPI CLOCK PORT GENERATOR master MISO 8-BIT SHIFT MOSI REGISTER SPICLK SPI CLOCK SS GENERATOR Rev. 03 — 12 March 2007 P89LPC932A1 slave MISO 8-BIT SHIFT MOSI REGISTER SPICLK SS 002aaa901 slave MISO 8-BIT SHIFT MOSI REGISTER SPICLK SPI CLOCK SS ...
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... Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core master MISO 8-BIT SHIFT MOSI REGISTER SPICLK SPI CLOCK port GENERATOR port Rev. 03 — 12 March 2007 P89LPC932A1 slave MISO 8-BIT SHIFT MOSI REGISTER SPICLK SS slave MISO 8-BIT SHIFT MOSI REGISTER SPICLK ...
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... NXP Semiconductors 7.23 Analog comparators Two analog comparators are provided on the P89LPC932A1. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logic 1 (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be confi ...
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... In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer than six CCLKs. P89LPC932A1_3 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Rev. 03 — 12 March 2007 P89LPC932A1 © NXP B.V. 2007. All rights reserved ...
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... Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog clock and the CPU is powered-down, the watchdog is disabled. The watchdog timer has a time-out period that ranges from a few few seconds. Please refer to the P89LPC932A1 User manual for more details. MOV WFEED1, #0A5H MOV WFEED2, #05AH ...
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... NXP Semiconductors 7.27 Data EEPROM The P89LPC932A1 has 512 B of on-chip data EEPROM. The data EEPROM is SFR based, byte readable, byte writable, and erasable (via row fill and sector fill). The user can read, write and fill the memory via SFRs and one interrupt. This data EEPROM provides 400000 minimum erase/program cycles for each byte. • ...
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... ICP is performed without removing the microcontroller from the system. The ICP facility consists of internal hardware resources to facilitate remote programming of the P89LPC932A1 through a two-wire serial interface. The ICP facility has made ICP in an embedded application—using commercially available programmers—possible with a minimum of additional expense in components and circuit board area. The ICP function uses fi ...
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... P89LPC932A1 through the serial port. This firmware is provided by NXP and embedded within each P89LPC932A1 device. The ISP facility has made ISP in an embedded application possible with a minimum of additional expense in components and circuit board area. The ISP function uses fi ...
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... Some user-configurable features of the P89LPC932A1 must be defined at power-up and therefore cannot be set by the program after start of execution. These features are configured through the use of the flash byte UCFG1. Please see the P89LPC932A1 User manual for additional details. 7.30 User sector security bytes There are eight User Sector Security Bytes on the P89LPC932A1 device ...
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... P89LPC932A1_3 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core [1] Conditions ) with respect based on package heat transfer, not device power consumption values”: Rev. 03 — 12 March 2007 P89LPC932A1 Min Max Unit 55 +125 C 65 +150 ...
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... I = 3 all ports, push-pull mode with respect [5] with respect [ th(HL) Rev. 03 — 12 March 2007 P89LPC932A1 [1] Typ Max 0.5 - 0.3V DD 0.6V 0.7V DD ...
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... Conditions 2.4 V < V < 3.6 V; with DD BOV = 1, BOPD = 0 specifications are measured using an external clock with the following functions disabled: comparators, for steady state (non-transient) limits on I Rev. 03 — 12 March 2007 P89LPC932A1 [1] Min Typ Max [ 450 2. ...
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... Figure 22 13T cy(CLK) see Figure 22 - see Figure 22 - see Figure 22 150 0 - see Figure 24, 25, 26 CCLK 4 CCLK see Figure 26, 27 250 Rev. 03 — 12 March 2007 P89LPC932A1 MHz Unit osc Max Min Max 7.557 7.189 7.557 MHz 480 280 480 ...
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... Figure 26 see Figure 26 see Figure 24, 25, 26 see Figure 24, 25, 0 26, 27 see Figure 24, 25, 26 see Figure 24, 25, 26 Rev. 03 — 12 March 2007 P89LPC932A1 MHz Unit osc Max Min Max - 250 - ns - 165 - ns - 250 - ns - 165 - ns - 250 - ns - 100 - ns - 100 - ns 120 0 ...
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... Figure 22 - see Figure 22 150 0 - see Figure 24, 25, 26 CCLK 4 CCLK see Figure 26, 27 250 see Figure 26, 27 250 Rev. 03 — 12 March 2007 P89LPC932A1 MHz Unit osc Max Min Max 7.557 7.189 7.557 MHz 480 280 480 ...
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... Figure 26 see Figure 24, 25, 26 see Figure 24, 0 25, 26, 27 see Figure 24, 25, 26 see Figure 24, 25, 26 Rev. 03 — 12 March 2007 P89LPC932A1 MHz Unit osc Max Min Max - 111 - ns - 167 - ns - 111 - ns - 167 - ns - 100 - ns - 100 - 160 ...
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... SPIF t SPICLKL t SPICLKH t t SPIF SPIR t SPICLKL t SPICLKH t t SPIDSU SPIDH MSB/LSB SPIDV SPIOH master MSB/LSB out Rev. 03 — 12 March 2007 P89LPC932A1 set TI valid valid valid valid set RI 002aaa906 t CHCX t CLCH T cy(clk) 002aaa907 t SPIR LSB/MSB SPIDV SPIR ...
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... SPIR t SPICLKL t SPICLKH t t SPIOH SPIOH t t SPIDV SPIDV slave MSB/LSB out t t SPIDH SPIDSU MSB/LSB in Rev. 03 — 12 March 2007 P89LPC932A1 t SPIR LSB/MSB SPIDV SPIDV t SPIR master LSB/MSB out 002aaa909 t SPIR t SPILAG t t SPIOH SPIDIS slave LSB/MSB out not defined ...
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... SPICLKH t t SPIOH SPIOH t t SPIDV SPIDV slave MSB/LSB out SPIDSU SPIDH SPIDSU MSB/LSB in Conditions Rev. 03 — 12 March 2007 P89LPC932A1 t SPIR t SPILAG t SPIDIS slave LSB/MSB out t t SPIDSU SPIDH LSB/MSB in 002aaa911 Min Typ Max 002aaa912 © ...
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... LI [1] This parameter is characterized, but not tested in production. P89LPC932A1_3 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Conditions Min - 0 [ < V < Rev. 03 — 12 March 2007 P89LPC932A1 Typ Max Unit - 0 250 500 ...
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... 0.81 11.58 11.58 10.92 10.92 12.57 1.27 0.66 11.43 11.43 9.91 9.91 12.32 0.032 0.456 0.456 0.43 0.43 0.495 0.05 0.026 0.450 0.450 0.39 0.39 0.485 REFERENCES JEDEC JEITA MS-018 EDR-7319 Rev. 03 — 12 March 2007 P89LPC932A1 detail ( max. 12.57 1.22 1.44 0.18 0.18 0.1 2.16 12.32 1.07 1.02 0.495 ...
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... 2.5 scale (1) ( 0.30 0.2 9.8 4.5 0.65 0.19 0.1 9.6 4.3 REFERENCES JEDEC JEITA MO-153 Rev. 03 — 12 March 2007 P89LPC932A1 detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 0.3 EUROPEAN PROJECTION SOT361-1 ...
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... 2.5 scale (1) ( 6.1 4.25 6.1 4.25 0.65 3.9 3.9 5.9 3.95 5.9 3.95 REFERENCES JEDEC JEITA MO-220 - - - Rev. 03 — 12 March 2007 P89LPC932A1 detail 0.75 0.05 0.1 0.1 0.05 0.50 EUROPEAN PROJECTION SOT788 ISSUE DATE 02-10-22 © NXP B.V. 2007. All rights reserved. ...
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... scale (1) ( 1.7 0.53 0.32 36 14.1 1.3 0.38 0.23 35 13.7 0.066 0.020 0.013 1.41 0.56 0.051 0.014 0.009 1.34 0.54 REFERENCES JEDEC JEITA MO-015 SC-510-28 Rev. 03 — 12 March 2007 P89LPC932A1 3.9 15.80 17.15 2.54 15.24 3.4 15.24 15.90 0.15 0.62 0.68 0.1 0.6 0.13 0.60 0.63 EUROPEAN PROJECTION SOT117 ...
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... Electrically Erasable Programmable Read-Only Memory ElectroMagnetic Interference Light Emitting Diode Phase-Locked Loop Pulse Width Modulator Random Access Memory Resistance-Capacitance Real-Time Clock Special Function Register Serial Peripheral Interface Universal Asynchronous Receiver/Transmitter Rev. 03 — 12 March 2007 P89LPC932A1 © NXP B.V. 2007. All rights reserved ...
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... Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Added new part type P89LPC932A1FN. P89LPC932A1_2 20050510 P89LPC932A1_1 20040720 P89LPC932A1_3 ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 03 — 12 March 2007 P89LPC932A1 © NXP B.V. 2007. All rights reserved ...
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... Internal reference voltage 7.23.2 Comparator interrupt . . . . . . . . . . . . . . . . . . . 38 7.23.3 Comparators and power reduction modes . . . 39 7.24 Keypad interrupt . . . . . . . . . . . . . . . . . . . . . . . 39 7.25 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 40 7.26 Additional features . . . . . . . . . . . . . . . . . . . . . 40 7.26.1 Software reset . . . . . . . . . . . . . . . . . . . . . . . . 40 7.26.2 Dual data pointers . . . . . . . . . . . . . . . . . . . . . 40 7.27 Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . 41 7.28 Flash program memory . . . . . . . . . . . . . . . . . 41 7.28.1 General description . . . . . . . . . . . . . . . . . . . . 41 7.28.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Rev. 03 — 12 March 2007 P89LPC932A1 continued >> © NXP B.V. 2007. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com P89LPC932A1 All rights reserved. Date of release: 12 March 2007 Document identifier: P89LPC932A1_3 ...