STM32F100C6 STMicroelectronics, STM32F100C6 Datasheet - Page 65

• Manufacturer Part Number: STM32F100C6
• Description: Mainstream Value line, ARM Cortex-M3 MCU with 32 Kbytes Flash, 24 MHz CPU, motor control and CEC functions
• Manufacturer: STMicroelectronics

Specifications of STM32F100C6

• Peripherals Supported: timers, ADC, SPIs, I2Cs, USARTs and DACs
• Conversion Range: 0 to 3.6 V
• 16-bit, 6-channel Advanced-control Timer: up to 6 channels for PWM output, dead time generation and emergency stop
• Systick Timer: 24-bit downcounter

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
SPI interface characteristics
Unless otherwise specified, the parameters given in
performed under the ambient temperature, f
conditions summarized in
Refer to
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 41.
1. Based on characterization, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
DuCy(SCK)
t
t
t
t
dis(SO)
t
w(SCKH)
t
w(SCKL)
su(NSS)
t
a(SO)
Symbol
1/t
t
t
t
t
t
t
h(NSS)
su(MI)
v(SO)
t
v(MO)
h(MO)
the data.
the data in Hi-Z
su(SI)
h(MI)
h(SO)
t
t
h(SI)
r(SCK)
f(SCK)
f
SCK
c(SCK)
(1)(2)
(1)
(1)(3)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Section 5.3.12: I/O current injection characteristics
(1)
(1)
(1)
SPI characteristics
SPI clock frequency
SPI clock rise and fall
time
SPI slave input clock
duty cycle
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time Slave mode, f
Data output disable time Slave mode
Data output valid time
Data output valid time
Data output hold time
Parameter
Table
Doc ID 16455 Rev 6
8.
Master mode
Slave mode
Capacitive load: C = 30 pF
Slave mode
Slave mode
Slave mode
Master mode, f
presc = 4
Master mode
Slave mode
Master mode
Slave mode
Slave mode (after enable edge)
Master mode (after enable
edge)
Slave mode (after enable edge)
Master mode (after enable
edge)
PCLKx
Conditions
PCLK
frequency and V
PCLK
Table 41
= 24 MHz
= 24 MHz,
for more details on the
are derived from tests
Electrical characteristics
DD
4t
2t
Min
PCLK
PCLK
30
15
supply voltage
50
5
5
5
4
2
2
0
3t
Max
PCLK
12
10
25
70
60
12
5
8
MHz
Unit
65/87
ns
ns
%