STM32L151C6 STMicroelectronics, STM32L151C6 Datasheet - Page 107

• Manufacturer Part Number: STM32L151C6
• Description: Ultra-low-power ARM Cortex-M3 MCU with 32 Kbytes Flash, 32 MHz CPU, LCD, USB
• Manufacturer: STMicroelectronics

Specifications of STM32L151C6

• Operating Power Supply Range: 1.65 V to 3.6 V (without BOR) or 1.8 V to 3.6 V (with BOR option)
• Temperature Range: –40 to 85 °C
• 4 Modes: Sleep, Low-power run (9 μA at 32 kHz), Low-power sleep (4.4 μA),Stop with RTC (1.45 μA), Stop (570 nA), Standby (300 nA)
• Ultralow Leakage Per I/o: 50 nA
• Fast Wakeup From Stop: 8 μs
• Core: ARM 32-bit Cortex™-M3 CPU
• Dma: 7-channel DMA controller, supporting timers, ADC, SPIs, I2Cs and USARTs

STM32L151xx, STM32L152xx
Table 66.
25-Feb-2011
Date
Document revision history (continued)
Revision
cont’d
4
Updated
Standby mode on page 55
from Stop).
Table 20: Typical and maximum timings in Low power modes on
page
Run mode; updated max values for Wakeup from Stop mode, regulator
in low power mode; updated max values for t
Table 21: Peripheral current consumption on page
for column Low power sleep and run; updated Flash values; renamed
ADC1 to ADC; updated I
I
concerning ADC.
Table 22: High-speed external user clock characteristics on page
added min value for t
max value for t
and max values.
Table 23: Low-speed external user clock characteristics on page
updated max value for I
Table 24: HSE 1-24 MHz oscillator characteristics on page
renamed i
I
Table 25: LSE oscillator characteristics (fLSE = 32.768 kHz) on
page
Table 26: HSI oscillator characteristics on page
and max values for ACC
Table 28: MSI oscillator characteristics on page
typ, and max values for D
Table 31: Flash memory characteristics on page
for t
Table 40: I/O AC characteristics on page
for 01, 10, and 11; updated min value; updated footnotes.
Table 51: ADC accuracy on page
the test conditions for ENOB, SINAD, SNR, and THD.
Table 53: DAC characteristics on page
added footnote 8.
Updated leakage value in
the
Added
supply pin during ADC
Added
Figure 28: Power supply and reference decoupling (VREF+ not
connected to
capacitors.
Figure 29: Power supply and reference decoupling (VREF+ connected
to
DD (RTC)
DD(HSE)
VDDA): replaced 10 nF capacitor with 100 nF capacitor.
prog
ADC.
Doc ID 17659 Rev 6
56: updated condition for Wakeup from Stop mode, regulator in
63: updated max value for I
Figure 27: Maximum dynamic current consumption on VREF+
Table 52: RAIN max for fADC = 16 MHz on page 88
.
.
and I
Table 19: Typical and maximum current consumptions in
2
as I
VDDA): replaced all 10 nF capacitors with 100 nF
DD (IWDG)
r(HSE)
HSE
and updated max value; updated max values for
/t
w(HSE)
f(HSE)
conversion.
; updated footnote 1 and 3; added foot note 2
L
HSI
DD (LCD)
.
VOLT(MSI)
Figure 26: Typical connection diagram using
(I
/t
.
OSC_IN rise or fall time; updated I
DD
w(HSE)
Changes
(WU from Standby) instead of (I
value; updated units; added values for
LSE
86: updated typ values and some of
.
OSC_IN high or low time; added
.
90: updated footnote 7 and
75: updated some max values
WUSTDBY
66: updated parameter,
65: updated some min
68: updated typ values
57: updated values
Revision history
.
62:
L
DD
for typ
107/109
60:
59:
(WU